单片CMOS 10.4 ghz锁相环

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015037

Dong-Jun Yang, K. O

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引用次数: 4

摘要

提出了一种采用0.18-/spl mu/m CMOS工艺实现的带256/257双模预分频器的10.4 ghz锁相环。带有4/5同步计数器的预分频器工作频率高达14 GHz。计数器通过使用反馈来实现这一点。当I/sub VCO/=8.1 mA时，锁相环和压控振荡器的相位噪声电平为-122 dBc/Hz。锁相环工作在9.7 - 10.4 GHz之间，在V/sub DD/=1.8 V时输出34 mA。

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A monolithic CMOS 10.4-GHz phase locked loop

A 10.4-GHz PLL with a 256/257 dual modulus prescaler implemented in a 0.18-/spl mu/m CMOS process is presented. The prescaler with a 4/5 synchronous counter operates up to 14 GHz. The counter achieves this by using feedback. The phase noise levels of the PLL and VCO at a 3-MHz offset with I/sub VCO/=8.1 mA are -122 dBc/Hz. The PLL operates between 9.7 10.4 GHz, while drawing 34 mA at V/sub DD/=1.8 V.

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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