一种采用循环流水线adc的位串行块并行接口的双目CMOS距离图像传感器

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015102

T. Kato, S. Kawahito, K. Kobayashi, H. Sasaki, T. Eki, T. Hisanaga

{"title":"一种采用循环流水线adc的位串行块并行接口的双目CMOS距离图像传感器","authors":"T. Kato, S. Kawahito, K. Kobayashi, H. Sasaki, T. Eki, T. Hisanaga","doi":"10.1109/VLSIC.2002.1015102","DOIUrl":null,"url":null,"abstract":"A binocular CMOS image sensor used with a pair of aligned-in-parallel optical systems for range imaging is implemented. Sixteen compact cyclic pipelined analog-to-digital converters are integrated per an image sensor. The dedicated processor starts 16/spl times/16 FFT when the first bit-serial block-parallel data is obtained. The image sensor produces a 16/spl times/16 range image from a pair of 256/spl times/256 images, together with the dedicated pipelined FFT processor, at the maximum pipeline performance.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"A binocular CMOS range image sensor with bit-serial block-parallel interface using cyclic pipelined ADCs\",\"authors\":\"T. Kato, S. Kawahito, K. Kobayashi, H. Sasaki, T. Eki, T. Hisanaga\",\"doi\":\"10.1109/VLSIC.2002.1015102\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A binocular CMOS image sensor used with a pair of aligned-in-parallel optical systems for range imaging is implemented. Sixteen compact cyclic pipelined analog-to-digital converters are integrated per an image sensor. The dedicated processor starts 16/spl times/16 FFT when the first bit-serial block-parallel data is obtained. The image sensor produces a 16/spl times/16 range image from a pair of 256/spl times/256 images, together with the dedicated pipelined FFT processor, at the maximum pipeline performance.\",\"PeriodicalId\":162493,\"journal\":{\"name\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-06-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.2002.1015102\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2002.1015102","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 15

摘要

设计了一种采用双平行对准光学系统的双目CMOS图像传感器，用于距离成像。每个图像传感器集成了16个紧凑的循环流水线模数转换器。当获得第一个位串行块并行数据时，专用处理器启动16/spl次/16 FFT。图像传感器从一对256/spl倍/256图像产生16/spl倍/16范围图像，与专用流水线FFT处理器一起，以最大的流水线性能。

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A binocular CMOS range image sensor with bit-serial block-parallel interface using cyclic pipelined ADCs

A binocular CMOS image sensor used with a pair of aligned-in-parallel optical systems for range imaging is implemented. Sixteen compact cyclic pipelined analog-to-digital converters are integrated per an image sensor. The dedicated processor starts 16/spl times/16 FFT when the first bit-serial block-parallel data is obtained. The image sensor produces a 16/spl times/16 range image from a pair of 256/spl times/256 images, together with the dedicated pipelined FFT processor, at the maximum pipeline performance.

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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