M. Sugawara, K. Ogasawara, M. Aoyama, M. Zwerg, S. Głowiński, Y. Kameyama, T. Yanagita, M. Fukaishi, S. Shimoyama, T. Ishibashi, T. Noma
{"title":"1.5 Gbps, 5150 ppm spread spectrum SerDes PHY with a 0.3 mW, 1.5 Gbps level detector for serial ATA","authors":"M. Sugawara, K. Ogasawara, M. Aoyama, M. Zwerg, S. Głowiński, Y. Kameyama, T. Yanagita, M. Fukaishi, S. Shimoyama, T. Ishibashi, T. Noma","doi":"10.1109/VLSIC.2002.1015045","DOIUrl":null,"url":null,"abstract":"We have successfully developed a 5150 ppm spread spectrum serializer/deserializer (SerDes) physical layer (PHY) chip compliant with the serial AT attachment (ATA), The device was fabricated by a 0.13 /spl mu/m, 1.5 V CMOS process and includes a self-running, pulse-swallow phase locked loop (PLL) to generate the transmit (TX) carrier, a triple loop tracking the PLL to recover the receive (RX) clock, and a 0.3 mW current-crossover level detector to detect the 1.5 Gbps carrier for initial communication.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"27","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2002.1015045","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 27
Abstract
We have successfully developed a 5150 ppm spread spectrum serializer/deserializer (SerDes) physical layer (PHY) chip compliant with the serial AT attachment (ATA), The device was fabricated by a 0.13 /spl mu/m, 1.5 V CMOS process and includes a self-running, pulse-swallow phase locked loop (PLL) to generate the transmit (TX) carrier, a triple loop tracking the PLL to recover the receive (RX) clock, and a 0.3 mW current-crossover level detector to detect the 1.5 Gbps carrier for initial communication.