Static pulsed bus for on-chip interconnects

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015051

M. Khellah, J. Tschanz, Y. Ye, S. Narendra, V. De

引用次数: 26

Abstract

Static Pulsed Bus (SPB) improves delay by 15%-25% or reduces energy by 12%-25% and peak current by 26%-34%, compared to the conventional static bus (SB) scheme, for 1500 μm to 4500 μm bus lengths in a 100 nm technology. Energy savings are maintained across all data activity factors.

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用于片上互连的静态脉冲总线

与传统的静态总线(SB)方案相比，静态脉冲总线(SPB)在100 nm工艺中，在1500 μm ~ 4500 μm总线长度范围内，延迟提高15% ~ 25%，能量降低12% ~ 25%，峰值电流降低26% ~ 34%。在所有数据活动因素中都保持节能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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