soi优化的64位高速CMOS加法器设计

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015062

Jae-Joon Kim, R. Joshi, C. Chuang, K. Roy

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引用次数: 9

摘要

提出了一种采用0.1 /spl mu/m部分耗尽绝缘体上硅(PD/SOI)技术的高速64位混合进位/进位选择加法器，关键路径延迟为346 ps。采用基于感测放大器的差分逻辑和源跟随器评估树，用于快速生成8位群进位。浮动体PD/SOI在8位群进位产生电路上的性能比体CMOS提高了24%。我们还证明了所提出的电路对PD/SOI中由浮体效应引起的噪声具有鲁棒性。

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SOI-optimized 64-bit high-speed CMOS adder design

Presents a high-speed 64-bit hybrid carry-lookahead/carry-select adder in 0.1 /spl mu/m partially depleted silicon-on-insulator (PD/SOI) technology with a critical path delay of 346 ps. Sense-amplifier based differential logic with source follower evaluation tree is used for fast generation of 8-bit group carry. Floating body PD/SOI shows 24% performance improvement over bulk CMOS for the 8-bit group carry generating circuit. We also show that the proposed circuit is robust to noise induced by floating body effect in PD/SOI.

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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