{"title":"An on-chip high-efficiency DC-DC converter with a compact timing edge control circuit","authors":"Ton Ogawa, S. Hatanaka, Kenji Taniguchi","doi":"10.1109/VLSIC.2002.1015104","DOIUrl":null,"url":null,"abstract":"We developed an on-chip DC-DC converter with a compact timing edge control circuit operating at high clock frequency. The circuit generates four states to control nearly ideal switchings of output transistors depending on the voltages sensed at two terminals across an off-chip output inductor. High efficiency can be achieved due to nearly exact timing edge control with the aid of a high frequency clock by eliminating the conventional dead time control circuit. The DC-DC converter is fabricated in 0.25 /spl mu/m CMOS process with single polysilicon and triple metal. The experimental results at 2.5 V output show efficiency over 90% with a off-chip filter consisting of a inductor of 220 /spl mu/H and a ceramic capacitor of 47 /spl mu/F. The converter has maximum efficiency of 93.3% with 29 mV ripple at 37 mA load current.","PeriodicalId":162493,"journal":{"name":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.2002.1015104","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12
Abstract
We developed an on-chip DC-DC converter with a compact timing edge control circuit operating at high clock frequency. The circuit generates four states to control nearly ideal switchings of output transistors depending on the voltages sensed at two terminals across an off-chip output inductor. High efficiency can be achieved due to nearly exact timing edge control with the aid of a high frequency clock by eliminating the conventional dead time control circuit. The DC-DC converter is fabricated in 0.25 /spl mu/m CMOS process with single polysilicon and triple metal. The experimental results at 2.5 V output show efficiency over 90% with a off-chip filter consisting of a inductor of 220 /spl mu/H and a ceramic capacitor of 47 /spl mu/F. The converter has maximum efficiency of 93.3% with 29 mV ripple at 37 mA load current.