1.2 Gbps/pin simultaneous bidirectional transceiver logic with bit deskew technique

Abstract

We have developed a simultaneous bidirectional transceiver logic -composed of a transmitter with an output level feedback pre-buffer and a receiver with two sense amplifiers and a hazard-free selector - that reduces the data jitter originating from three voltage level transmission. We also developed a bit deskew technique that takes into account the influence of switching noise to obtain the maximum timing margin in multi-pin operation. Stable throughput of 1.2 Gbps/pin was achieved in simultaneous 81-pin operation using a printed circuit board.