高速可重复使用SRAM核心的可编程和自动可调感测放大器激活方案和多复位地址驱动解码方案

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015039

T. Suzuki, S. Nakahara, S. Iwahashi, K. Higeta, K. Kanetani, H. Nambu, M. Yoshida, K. Yamaguchi

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引用次数: 8

摘要

描述了为满足各种SOC设计中可重用嵌入式SRAM核心的需求而开发的新方案。PAS通过使用程序和自动控制相结合来优化传感器放大器的激活时间。MRAD通过减少路径到路径延迟的波动来最小化时间开销。这些方案实验证明了0.5到1.4 V的宽工作范围和600 ps的访问时间。

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Programmable and automatically-adjustable sense-amplifier activation scheme and multi-reset address-driven decoding scheme for high-speed reusable SRAM core

Describes novel schemes developed to meet the demand for a reusable embedded SRAM core for application to a variety of SOC designs. PAS optimizes sense-amplifier activation timing by using the combination of a program and automatic control. MRAD minimizes timing-overhead by reducing the fluctuation of path-to-path delay. These schemes experimentally demonstrated a wide-operation range of 0.5 to 1.4 V and an access time of 600 ps.

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2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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