1 gb /s/引脚多千兆DRAM设计，具有低阻抗分层I/O架构

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015061

H. Fujisawa, T. Takahashi, H. Yoko, I. Fujii, Y. Takai, M. Nakamura

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引用次数: 7

摘要

提出了一种低阻抗分层I/O结构，可同时实现高速和低压dram。在这个体系结构中，在内存单元上使用划分的I/O线可以将I/O线的负载减少50%，并使读/写周期时间减少2.2 ns。通过结合分布式数据传输方案，我们在多gb DRAM中使用1.8 v电源，将访问时间缩短4 ns至8 ns，并实现了1 gb /s/引脚操作。

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1-Gb/s/pin multi-gigabit DRAM design with low impedance hierarchical I/O architecture

A low impedance hierarchical I/O architecture designed to realize both high-speed and low-voltage DRAMs is presented. In this architecture, use of the divided I/O lines over the memory cells reduces the load of I/O lines by 50% and enables a 2.2 ns reduction of the read/write cycle time. By combining the distributed data transfer scheme, we achieved a 4 ns reduction of the access time to 8 ns and 1-Gb/s/pin operation with a 1.8-V power supply in a multi-Gb DRAM.

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来源期刊

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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