1.2 Gbps/pin同时双向收发逻辑与位倾斜技术

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302) Pub Date : 2002-06-13 DOI:10.1109/VLSIC.2002.1015044

Y. Fujimura, T. Takahashi, S. Toyoshima, K. Nagashima, J. Baba, T. Matsumoto

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引用次数: 5

摘要

我们开发了一种同时双向收发器逻辑-由具有输出电平反馈预缓冲器的发射器和具有两个感测放大器和无危险选择器的接收器组成-减少了来自三个电压电平传输的数据抖动。我们还开发了一种位偏移技术，该技术考虑了开关噪声的影响，以在多引脚工作中获得最大的时间裕度。使用印刷电路板在同时81脚操作的情况下实现了1.2 Gbps/引脚的稳定吞吐量。

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1.2 Gbps/pin simultaneous bidirectional transceiver logic with bit deskew technique

We have developed a simultaneous bidirectional transceiver logic -composed of a transmitter with an output level feedback pre-buffer and a receiver with two sense amplifiers and a hazard-free selector - that reduces the data jitter originating from three voltage level transmission. We also developed a bit deskew technique that takes into account the influence of switching noise to obtain the maximum timing margin in multi-pin operation. Stable throughput of 1.2 Gbps/pin was achieved in simultaneous 81-pin operation using a printed circuit board.

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来源期刊

2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302)

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