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Adaptive frequency control technique for enhancing transient performance of DC-DC converters 提高DC-DC变换器暂态性能的自适应频率控制技术
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430273
Hong-Wei Huang, C. Hsieh, Ke-Horng Chen, S. Kuo
{"title":"Adaptive frequency control technique for enhancing transient performance of DC-DC converters","authors":"Hong-Wei Huang, C. Hsieh, Ke-Horng Chen, S. Kuo","doi":"10.1109/ESSCIRC.2007.4430273","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430273","url":null,"abstract":"An adaptive frequency control (AFC) technique is proposed for minimizing transient dropout voltage and response time of switching DC-DC converters. As we know, nonlinear fast- transient techniques with fixed switching frequency can effectively regulate the unstable output voltage back to steady-state within a short time. However, they suffer from oscillation problem because of large sourcing or sinking recovery current at output of error amplifier by fast transient circuit. Therefore, linear operation provided by AFC technique can dynamically and smoothly adjust the switching frequency, which is proportional to the output voltage variation, to regulate output voltage back to its steady-state value. In other words, AFC technique eliminates system and sub-harmonic oscillation scenarios. Experimental results demonstrate the transient dropout voltage is improved 37.8% when load current changes from 100 mA to 500 mA.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"SE-10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126574934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
An analog front-end with integrated notch filter for 3–5 GHz UWB receivers in 0.13 μm CMOS 一种集成陷波滤波器的模拟前端，用于0.13 μm CMOS的3-5 GHz UWB接收器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430265
Alessio Vallese, A. Bevilacqua, C. Sandner, M. Tiebout, A. Gerosa, A. Neviani
{"title":"An analog front-end with integrated notch filter for 3–5 GHz UWB receivers in 0.13 μm CMOS","authors":"Alessio Vallese, A. Bevilacqua, C. Sandner, M. Tiebout, A. Gerosa, A. Neviani","doi":"10.1109/ESSCIRC.2007.4430265","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430265","url":null,"abstract":"A 3-5 GHz UWB receiver front-end employs a notch filter to deal with out-of-band blockers coming from Wi- Fi systems. The front-end draws a total of 20 mA from a 1.5 V supply (excluding the notch filter) and features a 3-step variable gain, with a maximum gain of 25 dB. The notch Alter provides as much as 36 dB of attenuation with a power consumption penalty of less than 20% and improves the linearity of the circuit by at least 6 dB. An algorithm for the automatic tuning and calibration of the filter is also demonstrated.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116877985","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Design for millimeter-wave applications in silicon technologies 设计毫米波应用于硅技术
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430343
A. Cathelin, B. Martineau, N. Seller, S. Douyere, J. Gorisse, S. Pruvost, C. Raynaud, F. Gianesello, S. Montusclat, S. Voinigescu, A. Niknejad, D. Belot, J. Schoellkopf
{"title":"Design for millimeter-wave applications in silicon technologies","authors":"A. Cathelin, B. Martineau, N. Seller, S. Douyere, J. Gorisse, S. Pruvost, C. Raynaud, F. Gianesello, S. Montusclat, S. Voinigescu, A. Niknejad, D. Belot, J. Schoellkopf","doi":"10.1109/ESSCIRC.2007.4430343","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430343","url":null,"abstract":"This paper presents the potentialities of advanced BiCMOS and CMOS technologies for millimeter-wave applications. To begin, the target applications in these frequency bands are presented: from automotive cruise control radars to wireless links. Then, a large overview of the technological offer to address these applications is presented: SiGe BiCMOS, nanometer bulk and SOI CMOS technologies. This work focuses both on active and passive devices (BEOL) behavior to suit for design above 20 GHz. The paper continues with a presentation of several solutions for integrated circuits on the presented topic: front-end receiver blocks, transmission blocks and frequency synthesis solutions. An overview of state of the art silicon circuits is given. As a conclusion, perspectives regarding future challenges in terms of system integration and applications are discussed.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126708673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme 一个0.6 tbps, 16端口SRAM设计，具有2级管道和多级传感方案
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430308
K. Johguchi, Y. Mukuda, S. Izumi, H. Mattausch, T. Koide
{"title":"A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme","authors":"K. Johguchi, Y. Mukuda, S. Izumi, H. Mattausch, T. Koide","doi":"10.1109/ESSCIRC.2007.4430308","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430308","url":null,"abstract":"A 8-read, 8-write port, 64-Kbit, 32-bit word-length SRAM design with multi-bank architecture is reported. Using a 2-stage-pipeline, a multi-stage-sensing scheme and a 2-port SRAM cell, high speed and high stability access is achieved simultaneously. The fabricated test chip in 90-nm CMOS technology features 1.2 GHz maximum clock frequency, 0.91 mm Si-area, 0.6 Tbps random-access bandwidth, and 123 mW power dissipation at 1.2 GHz. In comparison with a previously reported 16-port SRAM a bit-area reduction by an order of magnitude is achieved.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121739257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A +100dB gain, rail-to-rail output, low distortion, low noise amplifier in BiCMOS technology 一个+100dB增益，轨对轨输出，低失真，低噪声的BiCMOS技术放大器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430339
P. Golden, P. Mole, Barry Harvey
{"title":"A +100dB gain, rail-to-rail output, low distortion, low noise amplifier in BiCMOS technology","authors":"P. Golden, P. Mole, Barry Harvey","doi":"10.1109/ESSCIRC.2007.4430339","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430339","url":null,"abstract":"This paper describes a rail to rail output low noise, highly linear operational amplifier implemented in 0.5 mum BiCMOS technology. A novel gain boosting technique applied to a folded cascode input stage allows a low frequency gain of over 100 dB to be achieved with a two stage design, while additionally allowing the input to sense common mode ground. The disadvantage incurred in the relatively high DC current consumption of the folded cascode input stage is somewhat mitigated by a novel interstage coupling technique allowing bias current to be shared. Two further distortion reducing features of the output stage are the compensation technique and the presence of complementary emitter followers.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126542351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of stress on various circuit characteristics in 65nm PDSOI technology 应力对65nm PDSOI技术中各种电路特性的影响
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430893
S. Suryagandh, Mayank Gupta, Zhiyuan Wu, S. Krishnan, M. Pelella, J. Goo, C. Thuruthiyil, J. An, Brian Q. Chen, N. Subba, L. Zamudio, J. Yonemura, A. Icel
{"title":"Impact of stress on various circuit characteristics in 65nm PDSOI technology","authors":"S. Suryagandh, Mayank Gupta, Zhiyuan Wu, S. Krishnan, M. Pelella, J. Goo, C. Thuruthiyil, J. An, Brian Q. Chen, N. Subba, L. Zamudio, J. Yonemura, A. Icel","doi":"10.1109/ESSDERC.2007.4430893","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430893","url":null,"abstract":"Logic performance is improved by creating more stress in the channel in advanced CMOS technologies. Impact of stress on different circuit blocks in a microprocessor chip has not been studied in detail. This paper presents a comprehensive study on the effects of stress and the corresponding process steps on various circuit characteristics. Analog behavior, hysteresis and noise properties are investigated to understand the effect of stress on them. These characteristics play important roles in determining the performances of analog/phy, I/O and PLL blocks respectively. It is shown that the type of process steps used for stress optimization can significantly alter the performance of various circuits.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128530631","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.2V, 7.5 μW, 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS 0.2V, 7.5 μW, 20 kHz ΣΔ调制器，90 nm CMOS, 69 dB信噪比
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430281
U. Wismar, D. Wisland, P. Andreani
{"title":"A 0.2V, 7.5 μW, 20 kHz ΣΔ modulator with 69 dB SNR in 90 nm CMOS","authors":"U. Wismar, D. Wisland, P. Andreani","doi":"10.1109/ESSCIRC.2007.4430281","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430281","url":null,"abstract":"This paper presents a frequency-to-digital SigmaDelta modulator designed in a digital 90nm CMOS process, operating with a supply voltage of 0.2 V. For a 7.5 muW power consumption, the SNR is 68.9 dB and the SNDR is 60.3 dB over a 20Hz-20kHz bandwidth. This work shows that the SNR/SNDR performance of this kind of SigmaDelta converter can be adjusted over a wide range, while maintaining a state-of-the-art flgure-of-merit of 82 fJ/conversion.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129307093","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits 多栅极场效应晶体管CMOS电路低功耗设计技术的效率
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430891
C. Pacha, K. von Arnim, F. Bauer, T. Schulz, W. Xiong, K. T. San, A. Marshall, T. Baumann, C. Cleavelin, K. Schruefer, J. Berthold
{"title":"Efficiency of low-power design techniques in Multi-Gate FET CMOS Circuits","authors":"C. Pacha, K. von Arnim, F. Bauer, T. Schulz, W. Xiong, K. T. San, A. Marshall, T. Baumann, C. Cleavelin, K. Schruefer, J. Berthold","doi":"10.1109/ESSDERC.2007.4430891","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430891","url":null,"abstract":"Energy dissipation, performance, and voltage scaling of Multi-Gate FET (MuGFET) based CMOS circuits are analyzed using product-representative test circuits composed of 10 k devices. The circuits are fabricated in a low power MuGFET CMOS technology, achieve clock frequencies of 370-500MHz at VDD=1.2V, and operate down to the subthreshold region. Voltage scalability of MuGFET circuits is superior to sub-100 nm planar CMOS circuits due to excellent short-channel effect control.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130564472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A millimeter-wave power amplifier with 25dB power gain and +8dBm saturated output power 具有25dB功率增益和+8dBm饱和输出功率的毫米波功率放大器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430297
Yanyu Jin, M. Sanduleanu, Eduardo Alarcon Rivero, J. Long
{"title":"A millimeter-wave power amplifier with 25dB power gain and +8dBm saturated output power","authors":"Yanyu Jin, M. Sanduleanu, Eduardo Alarcon Rivero, J. Long","doi":"10.1109/ESSCIRC.2007.4430297","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430297","url":null,"abstract":"A millimeter-wave power amplifier in 90-nm bulk CMOS technology is described. Microstrip transmission lines with ground sidewalls are used for signal distribution, matching and load resonators. The 3-stage PA comprises identical cascode stages with inter-stage matching. The measured peak power-gain is 25 dB at 52 GHz and 10 dB at 60 GHz with a -3 dB bandwidth of 46-53 GHz. Saturated output power is +8 dBm with a PAE of 7%. The -1 dB compression point is 5 dBm. Extra process options are not used (e.g. MIM capacitors, trimmed polysilicon resistors, or thick oxide FETs). The 1180times960 mum2 die consumes a total of 73 mA from a 1.5 V (plusmn10%) power supply.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131206846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Spectral PLL built-in self-test for integrated cellular transceivers 频谱锁相环内置自检集成蜂窝收发器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430345
Christian Muenker, R. Weigel
{"title":"Spectral PLL built-in self-test for integrated cellular transceivers","authors":"Christian Muenker, R. Weigel","doi":"10.1109/ESSCIRC.2007.4430345","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430345","url":null,"abstract":"A built-in self test (BIST) solution for the on-chip spectral verification of a 4 GHz phase-locked loop (PLL) is presented. The PLL is embedded in an integrated cellular RF transceiver in a 130 nm CMOS technology. The BIST blocks enable the detection of catastrophic and many parametric faults by measuring the PLL frequency response and checking for spurious sidebands and excessive in-band phase noise without external test equipment. Multi-tone stimuli with a spurious-free dynamic range (SFDR) of 60 dB are generated on-chip, the PLL RF response is demodulated and digitized in an on-chip digital FM discriminator. Spectral analysis is performed using digital narrowband filtering, achieving an SFDR of 45 dB. The fully digital BIST blocks require a chip area of only 0.06 mm2 and do not compromise the performance of the PLL itself.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132388938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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