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V-band balanced resistive mixer in 65-nm CMOS 65纳米CMOS v波段平衡电阻混频器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430318
M. Varonen, M. Kärkkäinen, K. Halonen
{"title":"V-band balanced resistive mixer in 65-nm CMOS","authors":"M. Varonen, M. Kärkkäinen, K. Halonen","doi":"10.1109/ESSCIRC.2007.4430318","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430318","url":null,"abstract":"We report a wideband resistive mixer fabricated in 65-nm CMOS for 60-GHz frequency range. The local oscillator signal balancing is implemented with an on-chip spiral balun. The broadband response of the balun enables wideband local oscillator tuning range. The mixer topology is suitable for both up- and downconversion. We present the on-wafer measurement results in both of these mixing modes. In downconversion, the mixer achieved 12.5 dB of conversion loss and +5 dBm of 1-dB input compression point. In upconversion, the measured conversion loss was 13.5 dB with -19 dBm of 1-dB output compression point. The local oscillator suppression was better than 34 dB for an LO frequency from 51 to 62 GHz. The size of the mixer including pads is 0.47 mm2.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134507757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Visual image processing RAM for fast 2-D data location search 视觉图像处理RAM快速二维数据位置搜索
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430309
Joo-Young Kim, Donghyun Kim, Seungjin Lee, Kwanho Kim, Seonghyun Jeon, H. Yoo
{"title":"Visual image processing RAM for fast 2-D data location search","authors":"Joo-Young Kim, Donghyun Kim, Seungjin Lee, Kwanho Kim, Seonghyun Jeon, H. Yoo","doi":"10.1109/ESSCIRC.2007.4430309","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430309","url":null,"abstract":"Visual image processing RAM (VIP-RAM) for fast 2-D data location search is proposed and implemented. It finds the local maximum location of 3times3 size window in single cycle latency using hierarchical 3-bank architecture. Each bank searches intermediate maximum from 3 32-bit data in a row, and top-level logic deduces the final maximum out of 3 32-bit data from 3 banks. Each memory bank includes special logic for 3 consecutive data read and 32-bit 3 input comparator. 8 VIP-RAMs are integrated in multi-core object recognition SoC and fabricated in 0.18 mum process. VIP-RAM is measured to operate at 200 MHz for 8.2 GOPS peak performance.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"212 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133997462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A wide tuning range Gm-C filter for multi-mode direct-conversion wireless receivers 用于多模直接转换无线接收机的宽调谐范围Gm-C滤波器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430282
Tien-Yu Lo, C. Hung, M. Ismail
{"title":"A wide tuning range Gm-C filter for multi-mode direct-conversion wireless receivers","authors":"Tien-Yu Lo, C. Hung, M. Ismail","doi":"10.1109/ESSCIRC.2007.4430282","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430282","url":null,"abstract":"A third-order channel selection filter for multi-mode direct-conversion receiver is presented. The filter is designed based on the Butterworth prototype with the target applications of bluetooth, cdma2000, wideband CDMA, and IEEE 802.11 a/b/g/n wireless LANs. Linear region MOS transistors are used to perform the voltage-to-current conversion. The wide tuning range can be achieved by the translinear loop followed by the linear voltage-to-current converter. Implemented in the TSMC 0.18-mum CMOS process, the measurement results show that the filter can operate with the cutoff frequency of 500 kHz to 20 MHz, and thus meet the requirement of different wireless applications. In the design, the maximum power consumption is 11.1 mW under a 1.2-V supply voltage. The figure of merit (FOM) is favorably compared with the other previously reported works.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134408184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Gb/s CDR circuit for large synchronous networks 用于大型同步网络的Gb/s CDR电路
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430358
S. Tontisirin, R. Tielert
{"title":"Gb/s CDR circuit for large synchronous networks","authors":"S. Tontisirin, R. Tielert","doi":"10.1109/ESSCIRC.2007.4430358","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430358","url":null,"abstract":"This paper presents a fully integrated clock and data recovery circuit (CDR) for clock distribution in large synchronous networks. By utilizing of a 2-loop architecture, clock and data recovery loop and clock jitter filtering loop, the CDR has no trade-off between its jitter tolerance and jitter filtering. In the CDR loop, a power-efficient 1/4-rate phase frequency detector is applied to provide inherent data demultiplexing and an operation without an external reference clock. In the clock jitter filtering loop, an integrated low jitter LC-VCO is used to improve the jitter of recovered clock. The CDR was implemented in 0.18 mum CMOS technology. It can provide a clock with jitter of 4.2ps rms from 2Gb/s serial data with ISI jitter 150ps P-P.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132868176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 10b 200MS/s pipelined folding ADC with offset calibration 一个10b200ms /s的流水线折叠ADC，带有偏移校准
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430268
Cheng-Chung Hsu, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee
{"title":"A 10b 200MS/s pipelined folding ADC with offset calibration","authors":"Cheng-Chung Hsu, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee","doi":"10.1109/ESSCIRC.2007.4430268","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430268","url":null,"abstract":"A 10b 200MS/s folding ADC is implemented with a cascaded folding factor of 4x5 to reduce the number of comparators. A simple offset calibration is developed to avoid the complex calibration loops, improving the settling behavior of the ADC. After calibration, the measured ENL is enhanced from +8M.5LSB to +1.4/-1.5LSB while the SNDR performance is improved from 43.9dB to 54.1dB at input frequency of 10.1MHz. Fabricated in 0.35/0.13 mum CMOS, the ADC occupies an area of 0.45 mm2. The analog and digital circuits dissipate 285mW at 3.3V and lmW at 1.2V power supply, respectively.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117112221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Low-noise variable-gain amplifier in 90-nm CMOS for TV on mobile 用于移动电视的90纳米CMOS低噪声变增益放大器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430320
L. Tripodi, H. Brekelmans
{"title":"Low-noise variable-gain amplifier in 90-nm CMOS for TV on mobile","authors":"L. Tripodi, H. Brekelmans","doi":"10.1109/ESSCIRC.2007.4430320","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430320","url":null,"abstract":"Presented is a low-noise variable-gain amplifier intended for handheld TV-on-mobile in the UHF band. The circuitry, implemented in 90-nm CMOS technology, is designed for compliance with MBRAI category 2 and 3 and for robustness against the high RF input levels caused by uplink signals from cellular and connectivity services integrated in the same handheld. The overall Noise Figure is kept low by employing lossless feedback in the VGA. The effect of a back- gate control to reduce the sensitivity of the amplifier characteristics to variations in supply voltage has been studied. The test chip realized exhibits 23 dB gain that can be stepped down with 2 dB resolution, 2.6 dB NF, a -5.4 dBm IIP3 at maximum gain and 40 mW power consumption at 1.2 V supply.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128947575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Power management for portable devices 便携式设备的电源管理
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430272
M. Manninger
{"title":"Power management for portable devices","authors":"M. Manninger","doi":"10.1109/ESSCIRC.2007.4430272","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430272","url":null,"abstract":"Today's portable devices combine wireless communication and navigation with consumer electronics. As a consequence, the computing power, the size of the display and the graphics operations of portable devices are increasing by a large amount. Even when changing to new process technologies for the processors, the power consumption often increases due to the higher operating frequencies. The battery technology developments are not improving by the same factor and as a result, intelligent power management becomes mandatory to achieve the required operating hours and days. In addition, the portable devices become smaller and slimmer which requires a reduction of the number and the size of the components. In this paper, a highly integrated power management IC will be presented and power management trends and requirements for portable devices will be discussed.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132369815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A 10-Gb/s CMOS fully integrated ILO-based CDR 10gb /s CMOS完全集成基于ilo的CDR
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430356
O. Mazouffre, B. Goumballa, M. Pignol, C. Neveu, Y. Deval, J. Bégueret
{"title":"A 10-Gb/s CMOS fully integrated ILO-based CDR","authors":"O. Mazouffre, B. Goumballa, M. Pignol, C. Neveu, Y. Deval, J. Bégueret","doi":"10.1109/ESSCIRC.2007.4430356","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430356","url":null,"abstract":"A CDR circuit dedicated to satellite embedded data link is presented. This circuit combines an injection locked oscillator, with a phase alignment circuit, to achieve the clock recovery. The circuit was designed in a 130 nm CMOS process from STMicroelectronics. The working range is from 9.6 Gbit/s up to 10.2 Gbit/s, the power dissipation is 94 mW under 1.2 V power supply. The measured eye opening is 60 ps and 240 mV with a BER lower than 1012.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"11 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120915559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiver 用于UWB-IR接收机的1 ghz输入带宽6位欠采样A/D转换器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430271
T. Nakagawa, T. Matsuura, E. Imaizumi, J. Kudoh, G. Ono, Masayuki Miyazaki, A. Maeki, Y. Ogata, Shinsuke Kobayashi, N. Koshizuka, K. Sakamura
{"title":"1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiver","authors":"T. Nakagawa, T. Matsuura, E. Imaizumi, J. Kudoh, G. Ono, Masayuki Miyazaki, A. Maeki, Y. Ogata, Shinsuke Kobayashi, N. Koshizuka, K. Sakamura","doi":"10.1109/ESSCIRC.2007.4430271","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430271","url":null,"abstract":"A 1-GHz input bandwidth 6-bit analog-to-digital (A/D) converter is described. The A/D converter is designed for an ultra-wideband impulse radio (UWB-IR) receiver that needs to digitize an input signal with a higher frequency than the sampling frequency. With the proposed under-sampling technique, sampling is executed with low-current consumption by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in another capacitor. In addition, a low-power comparator is proposed, which reduces bias current dynamically corresponding to its input voltage level. The A/D converter is implemented in a 0.18-mum CMOS process technology, which achieves an effective number of bits of 4.9 for input signals with frequencies greater than 1 GHz at 32 M samples/s, and consumes 0.89 mA at a 1.8-V supply. The converter occupies a 0.18 mm2 area.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125307712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A fast start-up 3GHz–10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS 90nm CMOS超宽带脉冲无线电快速启动3GHz-10GHz数字控制振荡器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430347
V. D. Heyn, G. V. D. Plas, J. Ryckaert, J. Craninckx
{"title":"A fast start-up 3GHz–10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS","authors":"V. D. Heyn, G. V. D. Plas, J. Ryckaert, J. Craninckx","doi":"10.1109/ESSCIRC.2007.4430347","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430347","url":null,"abstract":"A digitally controlled ring oscillator, key component of a UWB transceiver, is presented. The design supports the IEEE 802.15.4 standard for which all bands between 3 and 10 GHz can be synthesized with frequency steps as small as 4 MHz, it is to be embedded in a low power fast startup phase- aligned frequency-locked loop requiring a duty-cycled operation of the DCO with a settling time below 2 ns. The average power consumption ranges from 0.3 mW at 3 GHz up to 1 mW at 10 GHz in 90 nm IV digital CMOS.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127922312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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