Joo-Young Kim, Donghyun Kim, Seungjin Lee, Kwanho Kim, Seonghyun Jeon, H. Yoo
{"title":"Visual image processing RAM for fast 2-D data location search","authors":"Joo-Young Kim, Donghyun Kim, Seungjin Lee, Kwanho Kim, Seonghyun Jeon, H. Yoo","doi":"10.1109/ESSCIRC.2007.4430309","DOIUrl":null,"url":null,"abstract":"Visual image processing RAM (VIP-RAM) for fast 2-D data location search is proposed and implemented. It finds the local maximum location of 3times3 size window in single cycle latency using hierarchical 3-bank architecture. Each bank searches intermediate maximum from 3 32-bit data in a row, and top-level logic deduces the final maximum out of 3 32-bit data from 3 banks. Each memory bank includes special logic for 3 consecutive data read and 32-bit 3 input comparator. 8 VIP-RAMs are integrated in multi-core object recognition SoC and fabricated in 0.18 mum process. VIP-RAM is measured to operate at 200 MHz for 8.2 GOPS peak performance.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"212 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2007.4430309","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Visual image processing RAM (VIP-RAM) for fast 2-D data location search is proposed and implemented. It finds the local maximum location of 3times3 size window in single cycle latency using hierarchical 3-bank architecture. Each bank searches intermediate maximum from 3 32-bit data in a row, and top-level logic deduces the final maximum out of 3 32-bit data from 3 banks. Each memory bank includes special logic for 3 consecutive data read and 32-bit 3 input comparator. 8 VIP-RAMs are integrated in multi-core object recognition SoC and fabricated in 0.18 mum process. VIP-RAM is measured to operate at 200 MHz for 8.2 GOPS peak performance.