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An inductorless wideband balun-LNA in 65nm CMOS with balanced output 具有平衡输出的65nm CMOS无电感宽带平衡lna
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-12 DOI: 10.1109/ESSCIRC.2007.4430319
S. Blaakmeer, E. Klumperink, B. Nauta, D. Leenaerts
{"title":"An inductorless wideband balun-LNA in 65nm CMOS with balanced output","authors":"S. Blaakmeer, E. Klumperink, B. Nauta, D. Leenaerts","doi":"10.1109/ESSCIRC.2007.4430319","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430319","url":null,"abstract":"An inductorless LNA with active balun is designed for multi-standard radio applications between 100 MHz and 6 GHz. It exploits a combination of a common gate stage and a common source stage with replica biasing to maximize balanced operation. The NF is designed to be around 3 dB by using the noise canceling technique. Its best performance is achieved between 300 MHz to 3.5 GHz with gain and phase errors below 0.3 dB and plusmn2 degrees, 15 dB gain, S11<-14 dB, IIP3=0 dBm and IIP2 higher than +20 dBm at a total power consumption of 21 mW. The circuit is fabricated in a baseline 65 nm CMOS process, with an active area of only 0.01 mm2. The circuit simultaneously achieves impedance matching, noise canceling and a well balanced output.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133344593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 78
A low-power vector processor using logarithmic arithmetic for handheld 3d graphics systems 一个低功耗的矢量处理器，使用对数算法的手持式三维图形系统
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430286
Byeong-Gyu Nam, H. Yoo
{"title":"A low-power vector processor using logarithmic arithmetic for handheld 3d graphics systems","authors":"Byeong-Gyu Nam, H. Yoo","doi":"10.1109/ESSCIRC.2007.4430286","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430286","url":null,"abstract":"A low-power, high-performance 4-way 32-bit vector processor is developed for handheld 3D graphics systems. It contains a floating-point unified matrix, vector, and elementary function unit. By utilizing the logarithmic arithmetic, the unit achieves single-cycle throughput for all these operations except for the matrix-vector multiplication with 2-cycle throughput. The processor featured by this function unit, cascaded integer-float datapath, reconfiguration of datapath, operand forwarding in logarithmic domain, and vertex cache takes 9.7 mm2 in 0.18 mum CMOS technology and achieves 141 Mvertices/s for geometry transformation and 12.1 Mvertices/s for OpenGL transformation and lighting at 200 MHz with 86.6 mW power consumption.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"239 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115502050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Smart sensor design: The art of compensation and cancellation 智能传感器设计:补偿与抵消的艺术
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430251
K. Makinwa, M. Pertijs, J. V. Meer, J. H. Huijsing
{"title":"Smart sensor design: The art of compensation and cancellation","authors":"K. Makinwa, M. Pertijs, J. V. Meer, J. H. Huijsing","doi":"10.1109/ESSCIRC.2007.4430251","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430251","url":null,"abstract":"Smart sensors are systems in which sensors and dedicated interface electronics are integrated on the same chip, or at least in the same package. Due to the low-level analog output of typical sensors, designing interface electronics that \"does no harm,\" i.e. does not impair sensor performance, is quite challenging, especially in today's mainstream CMOS technology, whose inherent precision is limited by I/f noise and component mismatch. However, since most sensors are quite slow compared to transistors, dynamic techniques can often be used to trade speed or bandwidth for higher precision. Examples of such techniques are auto zeroing, chopping, dynamic element matching, switched-capacitor filtering and sigma-delta modulation. This paper describes the use of such dynamic techniques in the design and realization of state-of-the-art smart CMOS sensors for the measurement of temperature, wind velocity and magnetic field.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115184107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
A 90μW 15-bit ΔΣ ADC for digital audio 90μW 15位ΔΣ数字音频ADC
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430279
S. Pavan, N. Krishnapura, Ramalingam Pandarinathan, P. Sankar
{"title":"A 90μW 15-bit ΔΣ ADC for digital audio","authors":"S. Pavan, N. Krishnapura, Ramalingam Pandarinathan, P. Sankar","doi":"10.1109/ESSCIRC.2007.4430279","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430279","url":null,"abstract":"Architecture, circuit design details and measurement results for a 15 bit audio continuous-time DeltaSigma modulator (CTDSM) are given. The converter, designed in a 0.18 mum CMOS technology, achieves a dynamic range of 93.5 dB in a 24 kHz bandwidth and dissipates 90 muW from a 1.8 V supply. It features a third order active-RC loop filter, a very low power 4-bit flash quantizer and an efficient excess delay compensation scheme to reduce power dissipation.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122642210","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A clocked, regenerative comparator in 0.12μm CMOS with tunable sensitivity 灵敏度可调的0.12μm CMOS时钟再生比较器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430329
B. Goll, H. Zimmermann
{"title":"A clocked, regenerative comparator in 0.12μm CMOS with tunable sensitivity","authors":"B. Goll, H. Zimmermann","doi":"10.1109/ESSCIRC.2007.4430329","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430329","url":null,"abstract":"This paper presents a clocked, regenerative comparator in a 1.5V/0.1mum CMOS technology, where the sensitivity is tuned by separately adjusting the tail currents of the latch and the input amplifier. The comparator reaches a sensitivity of 3.9mV (2GHz) and 9.2mV (3GHz) to achieve a Bit Error Rate (BER) of 10-9 . The power consumption of the comparator is 422muW at 2GHz and 584muW at 3GHz. The simulated standard deviation of the offset is sigma=16.1mV. Finally a circuit extension is proposed, where only with an additional resistor the influence of noise and mismatch can be reduced.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121667761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Technical and economical trends in microelectronics 微电子技术和经济趋势
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430240
W. Ziebart
{"title":"Technical and economical trends in microelectronics","authors":"W. Ziebart","doi":"10.1109/ESSCIRC.2007.4430240","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430240","url":null,"abstract":"Product innovation has for a long time been directly correlated to scaling as the enabler for increasingly complex products, better performance and large productivity gains. The technical and economical limits of further miniaturization make an end to simple scaling as the primary driver for innovation. Furthermore, customers increasingly demand subsystems or system solutions that include more than one type of circuitry such as digital, RF or analog/mixed signal. This causes a fundamental paradigm shift in the semiconductor industry from technology orientation to application orientation - or even better to customer-orientation - which means that applications are becoming more and more dominant in driving innovations. Under this new paradigm, instead of technology roadmaps dominating the development of innovative products, the application requirements and customer needs determine which technology is best suited. An additional focus is arising on advanced packaging to enable smaller subsystems and system solutions. This paper analyzes why limits in performance, lithography and economics - and a shift in customer requirements - demand new types of innovation and discusses what will be the upcoming areas of interest for future research and development. The paradigm shift in the semiconductor industry is illustrated by recent examples from the communications and automotive segments that show how an application-oriented approach can achieve minimized system cost and optimized system functionality.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"262 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115830041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Architecture approaching the atomic scale 接近原子尺度的建筑
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430874
A. DeHon
{"title":"Architecture approaching the atomic scale","authors":"A. DeHon","doi":"10.1109/ESSDERC.2007.4430874","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430874","url":null,"abstract":"Both bottom-up and top-down techniques have been used to fabricate assemblies of devices and interconnect where key, density-defining feature sizes are on the order of ten atoms wide. We show how complete computing architectures can be constructed from these new techniques and building blocks despite high defect rates, extreme regularity requirements, and statistical assembly. We further highlight the paradigm shifts in integrated circuit design and architecture which appear necessary to accommodate these atomic-scale effects. Our estimates suggest a 10 nm full-pitch FPGA-like design can achieve one to two orders of magnitude greater logic density than ideal, defect-free lithographic scaling to 22 nm.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131607138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A stable compensation scheme for low dropout regulator in the absence of ESR 无ESR时低差调节器的稳定补偿方案
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430331
T. Kwok, W. Ki
{"title":"A stable compensation scheme for low dropout regulator in the absence of ESR","authors":"T. Kwok, W. Ki","doi":"10.1109/ESSCIRC.2007.4430331","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430331","url":null,"abstract":"A new compensation scheme for low dropout regulator (LDR) in relaxing the constraint on the equivalent series resistance (ESR) down to the value of zero from no load to full load current condition is presented. This is achieved by introducing a load-tracking zero that tracks with the moving output pole as the load current varies, and a level shift buffer reduces the size and capacitance of the power transistor. The load-tracking circuit ensures the stability in full load current range even in the absence of ESR. The proposed LDR is fabricated with a standard 0.35 mum CMOS technology. Measurement results at very small value ESR (10 mOmega) and output capacitor (0.47 muF), where this equivalent ESR zero is far beyond the compensation region of LDR, confirm the stability at ESR equivalent value to be zero. Also the proposed compensation scheme allows a wide range of ESR from equivalent 0 Omega to 20 Omega and load capacitor from 0.47 muF to 22 muF with a load current of 0 muA to 100 mA at dropout voltage of 0.2 V.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133755910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A 40–200 MHz programmable 4th-order Gm-C filter with auto-tuning system 一个40-200兆赫可编程的四阶Gm-C滤波器与自动调谐系统
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430283
A. Otín, S. Celma, C. Aldea
{"title":"A 40–200 MHz programmable 4th-order Gm-C filter with auto-tuning system","authors":"A. Otín, S. Celma, C. Aldea","doi":"10.1109/ESSCIRC.2007.4430283","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430283","url":null,"abstract":"A CMOS 40-200 MHz 4th-order Gm-C Butterworth filter with an automatic tuning system for both frequency and quality factor is presented. Constant-capacitance scaled Gm-C integrators features a technique leading to a wide transconductance tuning range. A compact dummy-based scheme is also incorporated in the design to maintain the integrating capacitance constant over all the programming range. The filter is based on Gm-C biquads and the experimental results in a low-cost pure digital 0.35 mum CMOS process have shown a dynamic range of 58 dB for THD<-40 dB with a single 2 V supply. The cut-off frequency is digitally programmable in the range of 40-200 MHz. An automatic tuning system for both characteristic cut-off frequency and Q-factor is used to compensate for process and temperature parameter variations.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"13 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124101212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept 超低功耗亚阈值MOS电流模式逻辑电路采用一种新颖的负载器件概念
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430304
A. Tajalli, E. Vittoz, Y. Leblebici, E. J. Brauer
{"title":"Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept","authors":"A. Tajalli, E. Vittoz, Y. Leblebici, E. J. Brauer","doi":"10.1109/ESSCIRC.2007.4430304","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430304","url":null,"abstract":"This article presents a novel and robust approach for implementing ultra-low power MOS current mode logic (MCML) circuits. To operate at very low bias currents, a simple and compact high resistance load device has been introduced. Operating in subthreshold regime, the circuit can be used in a very wide frequency range by adjusting the bias current without any need for resizing the devices. Measurements in 0.18 mum CMOS technology show that the proposed MCML circuit can be operated reliably with bias currents as low as 1 nA offering a significant improvement of the power-delay product compared to conventional CMOS gates. Simulations show that the proposed circuit exhibits faster response compared to the conventional MCML circuits with triode-mode PMOS load devices at low bias currents.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124772452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
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