{"title":"灵敏度可调的0.12μm CMOS时钟再生比较器","authors":"B. Goll, H. Zimmermann","doi":"10.1109/ESSCIRC.2007.4430329","DOIUrl":null,"url":null,"abstract":"This paper presents a clocked, regenerative comparator in a 1.5V/0.1mum CMOS technology, where the sensitivity is tuned by separately adjusting the tail currents of the latch and the input amplifier. The comparator reaches a sensitivity of 3.9mV (2GHz) and 9.2mV (3GHz) to achieve a Bit Error Rate (BER) of 10-9 . The power consumption of the comparator is 422muW at 2GHz and 584muW at 3GHz. The simulated standard deviation of the offset is sigma=16.1mV. Finally a circuit extension is proposed, where only with an additional resistor the influence of noise and mismatch can be reduced.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"125 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A clocked, regenerative comparator in 0.12μm CMOS with tunable sensitivity\",\"authors\":\"B. Goll, H. Zimmermann\",\"doi\":\"10.1109/ESSCIRC.2007.4430329\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a clocked, regenerative comparator in a 1.5V/0.1mum CMOS technology, where the sensitivity is tuned by separately adjusting the tail currents of the latch and the input amplifier. The comparator reaches a sensitivity of 3.9mV (2GHz) and 9.2mV (3GHz) to achieve a Bit Error Rate (BER) of 10-9 . The power consumption of the comparator is 422muW at 2GHz and 584muW at 3GHz. The simulated standard deviation of the offset is sigma=16.1mV. Finally a circuit extension is proposed, where only with an additional resistor the influence of noise and mismatch can be reduced.\",\"PeriodicalId\":121828,\"journal\":{\"name\":\"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference\",\"volume\":\"125 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2007.4430329\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2007.4430329","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
摘要
本文介绍了一种采用1.5V/0.1 ma CMOS技术的时钟再生比较器,通过单独调节锁存器和输入放大器的尾电流来调节灵敏度。比较器的灵敏度分别为3.9mV (2GHz)和9.2mV (3GHz),误码率(BER)为10-9。比较器的功耗在2GHz时为422muW,在3GHz时为584muW。偏移量的模拟标准差为sigma=16.1mV。最后提出了一种电路扩展方案,只需增加一个电阻,即可减小噪声和失配的影响。
A clocked, regenerative comparator in 0.12μm CMOS with tunable sensitivity
This paper presents a clocked, regenerative comparator in a 1.5V/0.1mum CMOS technology, where the sensitivity is tuned by separately adjusting the tail currents of the latch and the input amplifier. The comparator reaches a sensitivity of 3.9mV (2GHz) and 9.2mV (3GHz) to achieve a Bit Error Rate (BER) of 10-9 . The power consumption of the comparator is 422muW at 2GHz and 584muW at 3GHz. The simulated standard deviation of the offset is sigma=16.1mV. Finally a circuit extension is proposed, where only with an additional resistor the influence of noise and mismatch can be reduced.