A clocked, regenerative comparator in 0.12μm CMOS with tunable sensitivity

Abstract

This paper presents a clocked, regenerative comparator in a 1.5V/0.1mum CMOS technology, where the sensitivity is tuned by separately adjusting the tail currents of the latch and the input amplifier. The comparator reaches a sensitivity of 3.9mV (2GHz) and 9.2mV (3GHz) to achieve a Bit Error Rate (BER) of 10-9 . The power consumption of the comparator is 422muW at 2GHz and 584muW at 3GHz. The simulated standard deviation of the offset is sigma=16.1mV. Finally a circuit extension is proposed, where only with an additional resistor the influence of noise and mismatch can be reduced.