S. Blaakmeer, E. Klumperink, B. Nauta, D. Leenaerts
{"title":"An inductorless wideband balun-LNA in 65nm CMOS with balanced output","authors":"S. Blaakmeer, E. Klumperink, B. Nauta, D. Leenaerts","doi":"10.1109/ESSCIRC.2007.4430319","DOIUrl":null,"url":null,"abstract":"An inductorless LNA with active balun is designed for multi-standard radio applications between 100 MHz and 6 GHz. It exploits a combination of a common gate stage and a common source stage with replica biasing to maximize balanced operation. The NF is designed to be around 3 dB by using the noise canceling technique. Its best performance is achieved between 300 MHz to 3.5 GHz with gain and phase errors below 0.3 dB and plusmn2 degrees, 15 dB gain, S11<-14 dB, IIP3=0 dBm and IIP2 higher than +20 dBm at a total power consumption of 21 mW. The circuit is fabricated in a baseline 65 nm CMOS process, with an active area of only 0.01 mm2. The circuit simultaneously achieves impedance matching, noise canceling and a well balanced output.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"114 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"78","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2007.4430319","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 78
Abstract
An inductorless LNA with active balun is designed for multi-standard radio applications between 100 MHz and 6 GHz. It exploits a combination of a common gate stage and a common source stage with replica biasing to maximize balanced operation. The NF is designed to be around 3 dB by using the noise canceling technique. Its best performance is achieved between 300 MHz to 3.5 GHz with gain and phase errors below 0.3 dB and plusmn2 degrees, 15 dB gain, S11<-14 dB, IIP3=0 dBm and IIP2 higher than +20 dBm at a total power consumption of 21 mW. The circuit is fabricated in a baseline 65 nm CMOS process, with an active area of only 0.01 mm2. The circuit simultaneously achieves impedance matching, noise canceling and a well balanced output.