ESSCIRC 2007 - 33rd European Solid-State Circuits Conference最新文献_第2页

Clock jitter in class-D audio power amplifiers d类音频功率放大器的时钟抖动

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430338

M. Berkhout

引用次数: 14

A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology 基于65nm CMOS技术的7.5 gb /s SerDes阵列的低抖动时钟策略

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430359

P. Madeira, Marc-Andre LaCroix, J. Hogeboom

{"title":"A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology","authors":"P. Madeira, Marc-Andre LaCroix, J. Hogeboom","doi":"10.1109/ESSCIRC.2007.4430359","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430359","url":null,"abstract":"A low-jitter and low-power clocking strategy targeting a high-density multi-channel SerDes application is presented. A cascaded PLL architecture was devised in order to simultaneously meet the jitter generation requirements and distribute multiple clock phases to each transceiver segment. Multiple clock phases are generated and distributed to transceivers by a synchronized oscillator array (SOA), formed by multiple closed-loop ring oscillators (located in each transceiver segment). Each individual delay element is connected in parallel with its counterparts located in other segments of the array. The synchronized oscillator array spans the entire length of the SerDes macro, thus eliminating the need for expensive high-speed clock drivers. It is part of a wide-bandwidth PLL, which tracks a low-jitter clock generated from an on-chip wide-tuning range LC-PLL, locked to a low cost external reference. The long-term jitter measured at the output of a transmitter is approximately 0.33 ps rms. Integrated in STMicroelectronics' standard LP 65 nm CMOS process, the power consumption of the clock circuits in a 4 channel SerDes is 168 mW from a 1.2 V supply.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127240463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

An energy-efficient 1.5-Mbps wireless FSK transmitter with A ∑Δ-modulated phase rotator 一种具有∑Δ-modulated相位旋转器的1.5 mbps高效无线FSK发射机

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430348

Yao-Hong Liu, Tsung-Hsien Lin

引用次数: 9

A CMOS Operational Amplifier with Constant 68° phase margin over its whole range of noise-power trade-off programmability 在整个噪声-功率权衡可编程性范围内具有恒定68°相位裕度的CMOS运算放大器

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430340

Philipp Meier auf der Heide, C. Bronskowski, J. Tomasik, D. Schroeder

引用次数: 4

An 11.75-Gb/s combined decision feedback equalizer and clock data recovery circuit in 0.18-μm CMOS 基于0.18 μm CMOS的11.75 gb /s组合决策反馈均衡器和时钟数据恢复电路

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430353

Lijun Li, Michael M. Green

引用次数: 2

80 GHz low noise amplifiers in 65nm CMOS SOI 80 GHz低噪声放大器在65nm CMOS SOI

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430315

B. Martineau, A. Cathelin, F. Danneville, A. Kaiser, G. Dambrine, S. Lépilliet, F. Gianesello, D. Belot

引用次数: 26

A flexible, ultra-low power 35pJ/pulse digital back-end for a QAC UWB receiver 用于QAC UWB接收机的灵活、超低功耗35pJ/脉冲数字后端

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430287

M. Verhelst, W. Dehaene

引用次数: 8

An integrated switched-capacitor front-end for capacitive sensors with a wide dynamic range 用于宽动态范围电容式传感器的集成开关电容前端

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430328

A. Heidary, G. Meijer

引用次数: 3

A novel architecture for inductive proximity sensors using sigma delta modulation 一种采用σ δ调制的新型电感式接近传感器结构

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430299

S. Thoss, O. Machul, B. Hosticka

引用次数: 7

A 1 V 250 KPPS 90 NM CMOS pulse based transceiver for CM-range wireless communication 用于cm范围无线通信的1 V 250 KPPS 90 NM CMOS脉冲收发器

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430264

D. Guermandi, S. Gambini, J. Rabaey

引用次数: 21