A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology

Abstract

A low-jitter and low-power clocking strategy targeting a high-density multi-channel SerDes application is presented. A cascaded PLL architecture was devised in order to simultaneously meet the jitter generation requirements and distribute multiple clock phases to each transceiver segment. Multiple clock phases are generated and distributed to transceivers by a synchronized oscillator array (SOA), formed by multiple closed-loop ring oscillators (located in each transceiver segment). Each individual delay element is connected in parallel with its counterparts located in other segments of the array. The synchronized oscillator array spans the entire length of the SerDes macro, thus eliminating the need for expensive high-speed clock drivers. It is part of a wide-bandwidth PLL, which tracks a low-jitter clock generated from an on-chip wide-tuning range LC-PLL, locked to a low cost external reference. The long-term jitter measured at the output of a transmitter is approximately 0.33 ps rms. Integrated in STMicroelectronics' standard LP 65 nm CMOS process, the power consumption of the clock circuits in a 4 channel SerDes is 168 mW from a 1.2 V supply.