An 11.75-Gb/s combined decision feedback equalizer and clock data recovery circuit in 0.18-μm CMOS

Abstract

An 11.75-Gb/s combined DFE and CDR circuit in 0.18mum CMOS is presented. The feedback path of the DFE is merged with an Alexander phase detector resulting in reduced power and enhanced performance. It is capable of equalizing copper cable channels with up to 12dB loss at 5.875GHz Nyquist frequency and consumes 201mW with a 1.8 supply voltage.