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ESSCIRC 2007 - 33rd European Solid-State Circuits Conference最新文献

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Key directions and a roadmap for electrical design for manufacturability 可制造性电气设计的关键方向和路线图
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430252
A. Kahng
{"title":"Key directions and a roadmap for electrical design for manufacturability","authors":"A. Kahng","doi":"10.1109/ESSCIRC.2007.4430252","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430252","url":null,"abstract":"Semiconductor product value increasingly depends on \"equivalent scaling\" achieved by design and design-for-manufacturability (DFM) techniques. This talk addresses trends and a roadmap for \"equivalent scaling\" innovation at the design-manufacturing interface. The first part will discuss precepts of electrical DFM. What are dominant aspects of manufacturing variability and design requirements? Can designs match process, or must process inevitably adapt to designs? In what sense can concepts of \"virtual manufacturing\" or \"statistical optimization\" succeed in the design flow? How should design technology balance analyses that preserve value, versus optimizations that extend value? How should we balance preventions (correct by construction), versus early interventions, versus cures (construct by correction), versus \"do no harm\" opportunism? Or, tools that can model and predict well, versus tools that can make upstream assumptions come true? The second part will give a roadmap for electrical DFM technologies, motivated by emerging challenges (stress/strain engineering, mask errors, double-patterning lithography, etc.) and highlighting needs for les 45 nm nodes.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"332 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115977632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A fully integrated CMOS burst-mode upstream transmitter for gigabit-class passive optical network applications 一个完全集成的CMOS突发模式上游发射机，用于千兆级无源光网络应用
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430355
Y. Oh, Ho-Yong Kang, Kyoohyun Lim, Jongsik Kim, Sang-Gug Lee
{"title":"A fully integrated CMOS burst-mode upstream transmitter for gigabit-class passive optical network applications","authors":"Y. Oh, Ho-Yong Kang, Kyoohyun Lim, Jongsik Kim, Sang-Gug Lee","doi":"10.1109/ESSCIRC.2007.4430355","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430355","url":null,"abstract":"A fully integrated burst-mode upstream transmitter chip for gigabit-class passive optical network applications is implemented in 0.18mum CMOS technology. In order to control consecutive burst data, the transmitter proposed in this paper uses a reset mechanism with TX_enable as a burst envelope signal. The feedback from the monitoring photodiode (MPD) is separated by two independent paths for temperature compensation. The chip tested with chip-on-board configuration shows an average power of 2dBm with extinction ratio of above 12dB under 1.25Gb/s burst- mode operation. Based on the measurement, this work complies with the GPON ITU-T Recommendation G.984.2.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114794521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An integrated DC current regulator with high EMI suppression 具有高EMI抑制的集成直流电流调节器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430332
Jean-Michel Redouté, C. Walravens, S. V. Winckel, M. Steyaert
{"title":"An integrated DC current regulator with high EMI suppression","authors":"Jean-Michel Redouté, C. Walravens, S. V. Winckel, M. Steyaert","doi":"10.1109/ESSCIRC.2007.4430332","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430332","url":null,"abstract":"This paper presents an integrated DC current regulator using resistive trimming, which provides a high degree of immunity against conducted electromagnetic interference (EMI). While classic topologies generate erratic bias currents the moment EMI is injected into the circuit, this new topology continues to deliver the same reference DC current, whether or not EMI is present.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115171791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Exploring technology related design-space limitations of high performance network processing 探索与高性能网络处理的设计空间限制相关的技术
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430285
J. McCanny, S. Sezer, Máire O’Neill
{"title":"Exploring technology related design-space limitations of high performance network processing","authors":"J. McCanny, S. Sezer, Máire O’Neill","doi":"10.1109/ESSCIRC.2007.4430285","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430285","url":null,"abstract":"This paper summarizes numerous research activities in high-performance networks and network security processing, and explores technology related performance constraints such as critical performance limitations of circuit architectures, which are set by the semiconductor technologies.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115603030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOS 数字CMOS中可切换的低面积2.4 GHz和5ghz双带LNA
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430322
J. Borremans, P. Wambacq, G. V. D. Plas, Y. Rolain, M. Kuijk
{"title":"A switchable low-area 2.4-and-5 GHz dual-band LNA in digital CMOS","authors":"J. Borremans, P. Wambacq, G. V. D. Plas, Y. Rolain, M. Kuijk","doi":"10.1109/ESSCIRC.2007.4430322","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430322","url":null,"abstract":"Contemporary multistandard receivers implement the LNA functionality with either broadband LNAs, multiple separate LNAs or multiband LNAs. For system linearity, integration and area consumption, a multiband LNA could be preferable. This work demonstrates a switchable, 2.4-and-5 GHz dual-band feedback LNA, on an area as low as 40times160 mum2. Over 20 dB of gain is attained for a NF of 2.1 dB and a power consumption of 3.8 mW, indicating that the solution is suitable for low-cost multistandard receivers implemented in digital CMOS.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123654046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 0.35μm 50V CMOS sliding-mode control IC for buck converters 一种用于降压变换器的0.35μm 50V CMOS滑模控制IC
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430275
M. Hoyerby, M. Andersen, P. Andreani
{"title":"A 0.35μm 50V CMOS sliding-mode control IC for buck converters","authors":"M. Hoyerby, M. Andersen, P. Andreani","doi":"10.1109/ESSCIRC.2007.4430275","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430275","url":null,"abstract":"This paper presents a hysteretic (sliding mode) control IC for a buck DC/DC converter for use as an envelope tracking power supply to increase the efficiency of an RF power amplifier. The IC integrates a high-bandwidth error amplifier, a comparator with hysteresis, and a high-side driver for an external N-channel power MOSFET. The total control loop delay using the implemented IC is 35 ns, this is shown to be a 30% reduction compared to a state-of-the-art discrete IC based solution. The presented results also show that it is viable to integrate a 100 MHz operational amplifier on the same die as a high-voltage MOSFET driver operating with slew rates in excess of 5 V/ns. The IC is demonstrated in a tracking power supply with 30 W output power and 3 mus rise/fall time, running from a 40 V input. The complete IC, including pads, takes up 4 mm2 in a 0.35 mum 50 V CMOS process.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124121573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS 200mV至1.2V, 4.4MHz至6.3GHz, 48×42b 1R/1W可编程寄存器文件，65nm CMOS
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430307
A. Agarwal, N. Banerjee, S. Hsu, R. Krishnamurthy, K. Roy
{"title":"A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48×42b 1R/1W programmable register file in 65nm CMOS","authors":"A. Agarwal, N. Banerjee, S. Hsu, R. Krishnamurthy, K. Roy","doi":"10.1109/ESSCIRC.2007.4430307","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430307","url":null,"abstract":"This paper describes a 48times42b 1-read, 1-write ported register file which operates at supply voltage range of 1.2 V (6.1-6.3 GHz, 47 mW) down to 0.2 V (4-4.4 MHz, 0.01 mW) in 65 nm CMOS. Two programmable techniques, triple stacking and forced stacking are proposed which enable register files to operate at ultra low supply voltages while maintaining the performance comparable to conventional design at high supply voltages.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124376496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Single-grain Si thin-film transistors for analog and RF circuit applications 单粒硅薄膜晶体管模拟和射频电路应用
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430890
N. Saputra, M. Danesh, A. Baiano, R. Ishihara, J. Long, W. Metselaar, K. Beenakker, Nobuo Karaki, Y. Hiroshima, S. Inoue
{"title":"Single-grain Si thin-film transistors for analog and RF circuit applications","authors":"N. Saputra, M. Danesh, A. Baiano, R. Ishihara, J. Long, W. Metselaar, K. Beenakker, Nobuo Karaki, Y. Hiroshima, S. Inoue","doi":"10.1109/ESSDERC.2007.4430890","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430890","url":null,"abstract":"Single-grain (SG) Si-TFTs fabricated inside a location-controlled grain have SOI-like performance. To validate their potential for circuit application, key analog and RF building blocks are characterized. An operational amplifier (Opamp) and a voltage reference (Vref) demonstrate DC gain of 50 dB and power supply rejection ratio (PSRR) of 50 dB, respectively. With fT in the GHz range, SG-TFTs enable RF circuit design below 1 GHz. An RF cascode amplifier circuit is demonstrated.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129554481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 1V wireless transceiver for an ultra low power SoC for biotelemetry applications 用于生物遥测应用的超低功耗SoC的1V无线收发器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430262
A. Wong, Ganesh Kathiresan, Chung Kei Thomas Chan, Omar El-Jamaly, A. Burdett
{"title":"A 1V wireless transceiver for an ultra low power SoC for biotelemetry applications","authors":"A. Wong, Ganesh Kathiresan, Chung Kei Thomas Chan, Omar El-Jamaly, A. Burdett","doi":"10.1109/ESSCIRC.2007.4430262","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430262","url":null,"abstract":"This paper presents a IV RF transceiver implemented as part of an ultra low power system-on-chip (SoC), the Sensium , for wireless body area sensor network (WBASN) applications. Operating in the 862-870 MHz European short- range-device (SRD) or the 902-928 MHz North American Industrial, Scientific & Medical (ISM) frequency bands, the transceiver utilizes digital 2-level FSK modulation at a data rate of 50 kbit/s to provide wireless connectivity between target sensor nodes and a central base-station node. The wireless transceiver operates half-duplex and achieves -102 dBm receiver input sensitivity (for raw 1E-3 bit error rate) and up to -7 dBm transmitter output power through a single antenna port. It consumes 2.1 mA during receive and up to 2.6 mA during transmit from a 1.0 to 1.5 V supply. This surpasses state-of-the- art in terms of performance versus power consumption. It is fabricated in a 0.13 mum CMOS technology and occupies approximately 7 mm in a SoC die size of 4x4 mm .","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130616084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 45
An on-pixel FPN reduction method for a high dynamic range CMO S imager 高动态范围CMO S成像仪的逐像素FPN降阶方法
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430311
E. Labonne, G. Sicard, M. Renaudin
{"title":"An on-pixel FPN reduction method for a high dynamic range CMO S imager","authors":"E. Labonne, G. Sicard, M. Renaudin","doi":"10.1109/ESSCIRC.2007.4430311","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430311","url":null,"abstract":"A high dynamic range CMOS image sensor implementing a fixed pattern noise (FPN) reduction method is presented. The high dynamic range is reach through a logarithmic architecture pixel. An on-chip calibration method is implemented to reduce the FPN caused by process variations, weakness of this architecture. The basic principle is the calibration of each pixel against an in-pixel reference current in place of the diode photocurrent. Two pixel levels corresponding to the photocurrent and a known reference current become available for every pixel Then a double sampling technique allows removing offsets due to threshold voltage variations. An innovation of this work consists in the implementation of the current calibration source totally inside the pixel, allowing a better precision of the FPN compensation and lower power consumption. This FPN reduction method is performed while keeping only four transistors per pixel. A 128times128 pixels test chip has been designed and fabricated in 0.35 mum, 3.3 V CMOS standard technology. Pixel measures 10times10.6 mum2 with a fill factor of 33%. The dynamic range is up to 100dB with a frame rate up to 30 images per second and a measured FPN of 2.9% rms of the total dynamic range.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129950091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
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