发布求助
文献互助 智能选刊 最新文献

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference最新文献

筛选
英文 中文
A 1.2V 200-MS/s 10-bit folding and interpolating ADC in 0.13-μm CMOS 基于0.13 μm CMOS的1.2V 200-MS/s 10位折叠插值ADC
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430269
Yihui Chen, Qiuting Huang, T. Burger
{"title":"A 1.2V 200-MS/s 10-bit folding and interpolating ADC in 0.13-μm CMOS","authors":"Yihui Chen, Qiuting Huang, T. Burger","doi":"10.1109/ESSCIRC.2007.4430269","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430269","url":null,"abstract":"This paper presents a folding and interpolating ADC in a 0.13-mum CMOS technology, which achieves 10-bit resolution and 200-MS/s sample rate despite the limitations of a 1.2 V supply voltage. The converter employs an open-loop auto- zero technique to cancel preamplifier offsets, and preamplifiers provide sufficient gain to overcome offsets from the following stages, which enable 8.6ENOB (53.5 dB SNDR) to be reached. The IC measures 3.24 mm2 including pads and consumes 195 mW in total.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117088851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Frequency synthesis for a low-power 2.4 GHz receiver using a BAW oscillator and a relaxation oscillator 采用BAW振荡器和弛豫振荡器的低功耗2.4 GHz接收机的频率合成
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430349
J. Chabloz, D. Ruffieux, A. Vouilloz, P. Tortori, F. Pengg, Claude Müller, C. Enz
{"title":"Frequency synthesis for a low-power 2.4 GHz receiver using a BAW oscillator and a relaxation oscillator","authors":"J. Chabloz, D. Ruffieux, A. Vouilloz, P. Tortori, F. Pengg, Claude Müller, C. Enz","doi":"10.1109/ESSCIRC.2007.4430349","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430349","url":null,"abstract":"In this paper, a solution to realize local oscillators (LO) for a low power super-heterodyne receiver is presented. The first oscillator uses a bulk acoustic wave (BAW) resonator with high Q-factor. A quasi- harmonic quadrature relaxation oscillator with large tuning range is used to compensate for variations in the first oscillator and to cover the entire bandwidth for multiple channel selection.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113983976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A 5 GHz, 21 dBm output-IP3 resistive feedback LNA in 90-nm CMOS 一个5 GHz, 21 dBm输出ip3的90纳米CMOS阻性反馈LNA
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430321
B. Perumana, J. Zhan, S. Taylor, J. Laskar
{"title":"A 5 GHz, 21 dBm output-IP3 resistive feedback LNA in 90-nm CMOS","authors":"B. Perumana, J. Zhan, S. Taylor, J. Laskar","doi":"10.1109/ESSCIRC.2007.4430321","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430321","url":null,"abstract":"An inductor-less low noise amplifier is implemented in 90 nm CMOS using resistive feedback and non-linearity cancellation. In the high-linearity mode with non-linearity cancellation, the LNA achieves an output IP3 of 21.2 dBm and a noise figure of 2.9 dB at 5 GHz. In the low-noise mode, when the cancellation is switched off, it has a noise figure of 2.3 dB and an output IP3 of 14.3 dBm at 5 GHz. In both modes, the LNA has a gain above 24 dB with a bandwidth above 6.2 GHz. This circuit consumes 42 mW of power and occupies an active die area of 0.016 mm2.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126173203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Design considerations for low-noise, highly-linear millimeter-wave mixers in SiGe bipolar technology 采用SiGe双极技术的低噪声、高线性毫米波混频器的设计考虑
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430317
S. Trotta, B. Dehlink, H. Knapp, K. Aufinger, T. Meister, J. Böck, W. Simbürger, A. Scholtz
{"title":"Design considerations for low-noise, highly-linear millimeter-wave mixers in SiGe bipolar technology","authors":"S. Trotta, B. Dehlink, H. Knapp, K. Aufinger, T. Meister, J. Böck, W. Simbürger, A. Scholtz","doi":"10.1109/ESSCIRC.2007.4430317","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430317","url":null,"abstract":"This paper presents design considerations for millimeter-wave mixers based on the Gilbert cell. The theory has been validated by a test chip fabricated in a 200 GHz fT SiGe:C bipolar technology. The chip has been designed for applications at 76 GHz. The measured single-sideband noise figure (NFSSB) is 11.2 dB while the conversion gain is 15 dB with an input-referred 1 dB compression point (ICP) and an input-referred third-order intercept point (IIP3) of +2.5 dBm and +8.5 dBm, respectively. The chip consumes 61 mA at a supply voltage of 5.5 V.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126777333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A Sub-μA fast-settling current-programmed pixel circuit for AMOLED displays 一种用于AMOLED显示器的亚μA快速沉降电流编程像素电路
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430314
G. Chaji, A. Nathan
{"title":"A Sub-μA fast-settling current-programmed pixel circuit for AMOLED displays","authors":"G. Chaji, A. Nathan","doi":"10.1109/ESSCIRC.2007.4430314","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430314","url":null,"abstract":"Current-programmed active matrix organic light emitting diode (AMOLED) displays have been valued for their immunity to spatial mismatch, differential aging, and temperature variation. However, the long settling time particularly at small current levels and large parasitic capacitance can be a constraint. This paper presents a new current-programmed pixel circuit that improves the settling time while preserving the stability of current programming. The pixel circuit was fabricated in amorphous silicon technology. The settling time of the new pixel circuit can be as low as 20 mus whereas the settling time of conventional current-programmed pixel is more than 2 ms.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130071488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A CMOS Current-mode DC-DC converter with input and output voltage-independent stability and frequency characteristics utilizing a quadratic slope compensation scheme 一种采用二次斜率补偿方案的CMOS电流型DC-DC变换器，具有输入和输出电压无关的稳定性和频率特性
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430274
Kiyokazu Umimura, H. Sakurai, Y. Sugimoto
{"title":"A CMOS Current-mode DC-DC converter with input and output voltage-independent stability and frequency characteristics utilizing a quadratic slope compensation scheme","authors":"Kiyokazu Umimura, H. Sakurai, Y. Sugimoto","doi":"10.1109/ESSCIRC.2007.4430274","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430274","url":null,"abstract":"A CMOS Current-mode DC-DC converter using a quadratic slope compensation scheme is presented. The use of a quadratic slope instead of a conventional linear slope makes a damping factor and a frequency bandwidth of a current feedback loop independent of the converter's output voltage. Further designing the coefficient of the quadratic slope to be fully dependent of the input voltage, the damping factor and the frequency bandwidth become completely independent of both the input and output voltages. A test chip of a buck converter in a 5 MHz operation which uses a quadratic slope compensation scheme has been fabricated by using a 0.35 mum CMOS process. The evaluation results show that with a current capability of up to 500 mA the frequency characteristics of the total loop are constant when the input and output voltages change from 3.3 V to 2.5 V and from 2.5 V down to 0.5 V, respectively, and also that the recovery time is 50 mus with a peak voltage deviation of less than 50 mV for load current changes from 20 mA to 200 mA and vice versa.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114121255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Statistical modeling for the minimum standby supply voltage of a full SRAM array 全SRAM阵列最小备用电源电压的统计建模
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430327
Jiajing Wang, Amith Singhee, Rob A. Rutenbar, B. Calhoun
{"title":"Statistical modeling for the minimum standby supply voltage of a full SRAM array","authors":"Jiajing Wang, Amith Singhee, Rob A. Rutenbar, B. Calhoun","doi":"10.1109/ESSCIRC.2007.4430327","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430327","url":null,"abstract":"This paper presents two fast and accurate methods to estimate the lower bound of supply voltage scaling for standby SRAM/cache leakage power reduction of an SRAM array. The data retention voltage (DRV) defines the minimum supply voltage for a cell to hold its state. Within-die variation causes a statistical distribution of DRV for individual cells in a memory array, and cells far out the tail (i.e. >6sigma) limit the array DRV for large memories. We present two statistical methods to estimate the tail of the DRV distribution. First, we develop a new statistical model based on the connection between DRV and static noise margin (SNM). Second, we apply our Statistical Blockade tool to obtain fast Monte-Carlo simulation and a generalized Pareto distribution (GPD) model for comparison. Both the new model and the GPD model offer a high accuracy (<2% error) and a huge speed-up (>104times for 1 G-b memory) over Monte-Carlo simulation. In addition, both models show a very close agreement with each other at the tail even beyond 7sigma.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116189844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
Power combining techniques for RF and mm-wave CMOS power amplifiers 射频和毫米波CMOS功率放大器的功率组合技术
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1007/978-1-4020-8263-4_7
P. Reynaert, A. Niknejad
{"title":"Power combining techniques for RF and mm-wave CMOS power amplifiers","authors":"P. Reynaert, A. Niknejad","doi":"10.1007/978-1-4020-8263-4_7","DOIUrl":"https://doi.org/10.1007/978-1-4020-8263-4_7","url":null,"abstract":"","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124070731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 65nm CMOS multi-standard, multi-band mobile TV tuner 一个65nm CMOS多标准，多频段移动电视调谐器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430333
K. Vavelidis, I. Vassiliou, N. Haralabidis, A. Kyranas, Y. Kokolakis, S. Bouras, G. Kamoulakos, C. Kapnistis, S. Kavadias, N. Kanakaris, E. Metaxakis, Christos Kokozidis, H. Peyravi
{"title":"A 65nm CMOS multi-standard, multi-band mobile TV tuner","authors":"K. Vavelidis, I. Vassiliou, N. Haralabidis, A. Kyranas, Y. Kokolakis, S. Bouras, G. Kamoulakos, C. Kapnistis, S. Kavadias, N. Kanakaris, E. Metaxakis, Christos Kokozidis, H. Peyravi","doi":"10.1109/ESSCIRC.2007.4430333","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430333","url":null,"abstract":"A direct conversion, 65 nm CMOS multi-standard TV tuner is presented, which is compliant with several digital terrestrial, fixed and mobile TV standards (DVB-T, DVB-H, T-DMB and ISDB-T, including 1-3 segment). The tuner achieves a 3/3/2.8 dB NF at VHF, UHF and L-band respectively, while consuming less than 140 mW in DVB-T mode. By using integrated transformers, both single-ended and differential RF inputs are supported. Multi-standard capability is enabled by programmable channel-select filters and a Sigma-Delta fractional-N synthesizer.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132406070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A single die 124dB stereo audio delta sigma ADC with 111dB THD 单片124dB立体声δ σ ADC, THD为111dB
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430291
YuQing Yang, T. Sculley, J. Abraham
{"title":"A single die 124dB stereo audio delta sigma ADC with 111dB THD","authors":"YuQing Yang, T. Sculley, J. Abraham","doi":"10.1109/ESSCIRC.2007.4430291","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430291","url":null,"abstract":"A high performance, low power consumption, single die stereo delta sigma ADC is designed for professional audio and high precision measurement applications. A single loop, fifth-order, thirty-three level delta-sigma analog modulator with positive and negative feedforward path is implemented. An interpolated multilevel quantizer with unevenly weighted quantization levels replaces a conventional 5-bit flash type quantizer in this design. These new techniques suppress signal dependent energy inside the delta sigma loop, reduce internal channel coupling and power consumption. Integrated with an on-chip bandgap reference circuit and decimation filter, the ADC achieves 124 dB dynamic range (A-weighted), -111 dB THD over 20 kHz bandwidth. Inter-channel isolation is 130 dB. Total power consumption is less than 330 mW.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114957080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信