基于0.18 μm CMOS的11.75 gb /s组合决策反馈均衡器和时钟数据恢复电路

ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI:10.1109/ESSCIRC.2007.4430353

Lijun Li, Michael M. Green

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引用次数: 2

摘要

提出了一种基于0.18 μ m CMOS的11.75 gb /s DFE和CDR组合电路。DFE的反馈路径与亚历山大鉴相器合并，降低了功率，提高了性能。它能够在5.875GHz奈奎斯特频率下均衡高达12dB损耗的铜电缆通道，在1.8电源电压下消耗201mW。

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An 11.75-Gb/s combined decision feedback equalizer and clock data recovery circuit in 0.18-μm CMOS

An 11.75-Gb/s combined DFE and CDR circuit in 0.18mum CMOS is presented. The feedback path of the DFE is merged with an Alexander phase detector resulting in reduced power and enhanced performance. It is capable of equalizing copper cable channels with up to 12dB loss at 5.875GHz Nyquist frequency and consumes 201mW with a 1.8 supply voltage.

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ESSCIRC 2007 - 33rd European Solid-State Circuits Conference

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