Cheng-Chung Hsu, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee
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引用次数: 19
摘要
一个10b 200MS/s的折叠ADC实现了4 × 5的级联折叠因子，以减少比较器的数量。开发了一种简单的偏置校准方法，避免了复杂的校准回路，改善了ADC的沉降性能。校准后，测量的ENL从+8M增强。在输入频率为10.1MHz时，SNDR性能从43.9dB提高到54.1dB。该ADC采用0.35/0.13 mm CMOS制造，占地面积为0.45 mm2。模拟电路和数字电路分别在3.3V和1.2V电源下耗散285mW和lmW。
A 10b 200MS/s pipelined folding ADC with offset calibration
A 10b 200MS/s folding ADC is implemented with a cascaded folding factor of 4x5 to reduce the number of comparators. A simple offset calibration is developed to avoid the complex calibration loops, improving the settling behavior of the ADC. After calibration, the measured ENL is enhanced from +8M.5LSB to +1.4/-1.5LSB while the SNDR performance is improved from 43.9dB to 54.1dB at input frequency of 10.1MHz. Fabricated in 0.35/0.13 mum CMOS, the ADC occupies an area of 0.45 mm2. The analog and digital circuits dissipate 285mW at 3.3V and lmW at 1.2V power supply, respectively.
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