A 10b 200MS/s pipelined folding ADC with offset calibration

Abstract

A 10b 200MS/s folding ADC is implemented with a cascaded folding factor of 4x5 to reduce the number of comparators. A simple offset calibration is developed to avoid the complex calibration loops, improving the settling behavior of the ADC. After calibration, the measured ENL is enhanced from +8M.5LSB to +1.4/-1.5LSB while the SNDR performance is improved from 43.9dB to 54.1dB at input frequency of 10.1MHz. Fabricated in 0.35/0.13 mum CMOS, the ADC occupies an area of 0.45 mm2. The analog and digital circuits dissipate 285mW at 3.3V and lmW at 1.2V power supply, respectively.