T. Nakagawa, T. Matsuura, E. Imaizumi, J. Kudoh, G. Ono, Masayuki Miyazaki, A. Maeki, Y. Ogata, Shinsuke Kobayashi, N. Koshizuka, K. Sakamura
{"title":"1-GHz Input bandwidth 6-bit under-sampling A/D converter for UWB-IR receiver","authors":"T. Nakagawa, T. Matsuura, E. Imaizumi, J. Kudoh, G. Ono, Masayuki Miyazaki, A. Maeki, Y. Ogata, Shinsuke Kobayashi, N. Koshizuka, K. Sakamura","doi":"10.1109/ESSCIRC.2007.4430271","DOIUrl":null,"url":null,"abstract":"A 1-GHz input bandwidth 6-bit analog-to-digital (A/D) converter is described. The A/D converter is designed for an ultra-wideband impulse radio (UWB-IR) receiver that needs to digitize an input signal with a higher frequency than the sampling frequency. With the proposed under-sampling technique, sampling is executed with low-current consumption by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in another capacitor. In addition, a low-power comparator is proposed, which reduces bias current dynamically corresponding to its input voltage level. The A/D converter is implemented in a 0.18-mum CMOS process technology, which achieves an effective number of bits of 4.9 for input signals with frequencies greater than 1 GHz at 32 M samples/s, and consumes 0.89 mA at a 1.8-V supply. The converter occupies a 0.18 mm2 area.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2007.4430271","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
A 1-GHz input bandwidth 6-bit analog-to-digital (A/D) converter is described. The A/D converter is designed for an ultra-wideband impulse radio (UWB-IR) receiver that needs to digitize an input signal with a higher frequency than the sampling frequency. With the proposed under-sampling technique, sampling is executed with low-current consumption by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in another capacitor. In addition, a low-power comparator is proposed, which reduces bias current dynamically corresponding to its input voltage level. The A/D converter is implemented in a 0.18-mum CMOS process technology, which achieves an effective number of bits of 4.9 for input signals with frequencies greater than 1 GHz at 32 M samples/s, and consumes 0.89 mA at a 1.8-V supply. The converter occupies a 0.18 mm2 area.