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ESSCIRC 2007 - 33rd European Solid-State Circuits Conference最新文献

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A mixed-signal readout chip for a 7-cell Si-Drift detector in 0.35-μm BiCMOS technology 用于0.35 μm BiCMOS技术的7 cell Si-Drift检测器的混合信号读出芯片
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430302
I. Diehl, K. Hansen, C. Reckleben
{"title":"A mixed-signal readout chip for a 7-cell Si-Drift detector in 0.35-μm BiCMOS technology","authors":"I. Diehl, K. Hansen, C. Reckleben","doi":"10.1109/ESSCIRC.2007.4430302","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430302","url":null,"abstract":"This paper describes a mixed-signal seven-channel ASIC in 0.35-mum BiCMOS technology for the readout of Si-drift detectors used in X-ray spectroscopy. An integral count rate of more than four million pulses per second can be achieved. Count rate- and photon energy-related changes of the input pulse shape are compensated by a baseline-holding circuit, where the baseline instability remains below 1%. Within an input dynamic range between 1.9 mV and 7.2 mV a non-linearity below 1% can be reached. The equivalent input-noise voltage amounts to 31 muVrms. At maximum output voltage a channel-to-channel crosstalk of ~0.3% was measured. The power consumption of the readout chip is ~15 mW per channel. The functionalities of the main circuit blocks as well as experimental results are presented.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126915055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A high bandwidth power scaleable sub-sampling 10-bit pipelined ADC with embedded sample and hold 一个高带宽功率可扩展的10位子采样流水线ADC，具有嵌入式采样和保持器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430270
I. Ahmed, D. Johns
{"title":"A high bandwidth power scaleable sub-sampling 10-bit pipelined ADC with embedded sample and hold","authors":"I. Ahmed, D. Johns","doi":"10.1109/ESSCIRC.2007.4430270","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430270","url":null,"abstract":"A pipelined ADC architecture for use in sub-sampled systems which has its power scaleable with down sampled bandwidth is presented. Using a technique developed to eliminate the front end sample and hold, a power savings of >20% is achieved compared to a previous design. A technique to improve the settling behavior of Rapid Power on Opamps is also presented. Measured results in 1.8V 0.18 mum CMOS verify the removal of the front end sample and hold does not cause gross MSB errors for input frequencies higher than 267 MHz. With fs=50 MS/s, for fin=79 MHz the SNDR is 51.5 dB, and with fs=4.55 MS/s for fin=267 MHz the SNDR is 52.2 dB.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114469805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A power amplifier driver using self-oscillating pulse-width modulators 一种使用自振荡脉宽调制器的功率放大器驱动器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430323
W. Laflere, M. Steyaert, J. Craninckx
{"title":"A power amplifier driver using self-oscillating pulse-width modulators","authors":"W. Laflere, M. Steyaert, J. Craninckx","doi":"10.1109/ESSCIRC.2007.4430323","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430323","url":null,"abstract":"A polar transmitter for use with non-constant envelope signals is presented. Techniques for efficient behavior of both the amplitude (AM) and phase (PM) path are introduced. The envelope linearization technique is based on asynchronous pulse-width modulation of a phase-modulated RF signal. The efficiency of the switching amplifier is less dependent of the output power, compared to class B operation. Using a self-oscillating, asynchronous type of pulse-width modulator, the spurs are concentrated in narrow bands well separated from the signal band. These switching spurs are filtered out by the filters already present in the transmitter. The feasibility of this RF-pulse-width-modulation is proven by measurements with UMTS-signals on a prototype in 0.18 mum CMOS, yielding a peak output power of 8.26 dBm and a drain efficiency of 35%. In the phase-modulation path of the polar transmitter, injection locking of an oscillator is used as a single-stage high- gain amplifier. Avoiding multiple stages and related power loss improves the overall power efficiency.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121399321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 550mV 8dBm IIP3 4pth order analog base band filter for WLAN receivers 用于WLAN接收器的550mV 8dBm IIP3 4阶模拟基带滤波器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430352
M. Matteis, S. D’Amico, V. Giannini, A. Baschirotto
{"title":"A 550mV 8dBm IIP3 4pth order analog base band filter for WLAN receivers","authors":"M. Matteis, S. D’Amico, V. Giannini, A. Baschirotto","doi":"10.1109/ESSCIRC.2007.4430352","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430352","url":null,"abstract":"In this paper a 4th order low-pass continuous- time filter for a WLAN receiver is presented. The filter is designed to satisfy high-linearity performance while operating at very-low supply voltage. An improved bias circuit is used to operate with different opamp input and output common-mode voltages. The filter is realized in a standard 0.13 mum CMOS technology with VTHNap250 mV and VTHPap300 mV. The filter is optimally operating with supply voltage as low as 550 mV and slightly below. The filter architecture is composed by two active Gm-RC biquadratic cells, which use a single opamp per-cell with a unity-gain-bandwidth comparable to the filter cut-off frequency. This reduces the total cell power consumption. The -3 dB frequency is at 12 MHz (for WLAN applications) and this is higher than any other low-voltage continuous-time filter. The -3 dB frequency can be adjusted by means of a digitally- controlled capacitance array. The filter total area occupancy is 0.47 mm2 and the total power consumption is 3.4 mW from a single 550 mV supply. A 8 dBm-in-band IIP3 and a 13.3 dBm-out-of-band IIP3 demonstrate the validity of the proposal.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117286581","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS 基于0.18 μm CMOS的10gb /秒无锁电流模式逻辑(CML)模拟决策反馈均衡器(ADFE)
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430354
S. Chandramouli, F. Bien, Hyoungsoo Kim, E. Gebara, J. Laskar
{"title":"A 10-Gb/sec unclocked current-mode logic (CML) analog decision-feedback equalizer (ADFE) in 0.18-μm CMOS","authors":"S. Chandramouli, F. Bien, Hyoungsoo Kim, E. Gebara, J. Laskar","doi":"10.1109/ESSCIRC.2007.4430354","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430354","url":null,"abstract":"An unclocked analog decision-feedback equalizer (ADFE) is implemented in a 0.18-mum 40 GHz ft CMOS process to equalize legacy FR-4 backplane channels at 8~10-Gb/sec. The critical first feedback-loop latency requirement of the DFE is met by using a novel unclocked feedback topology and current-mode logic (CML) circuit building blocks. The circuit consists of a 4-tap linear analog feed-forward filter that cancels pre-cursor inter-symbol interference (ISI) to partially open the eye and a novel 1-tap analog tunable CML feedback filter that enables cancellation of the first post-cursor at 10-Gb/sec without the use of smaller process nodes or speculative techniques. The chip with pads occupies 1.04 mm2 and draws 240 mA DC current from a 1.8 V supply at a typical process corner. The ADFE is used to equalize 20 inches of FR-4 backplane traces at 8-Gb/sec and 10-Gb/sec.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129518820","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 5nV/√Hz-IRN, 78dB-gain-range, 78dB-DR multi-standard baseband chain for Bluetooth, UMTS and WLAN 5nV/√Hz-IRN, 78db增益范围，78dB-DR多标准基带链，适用于蓝牙，UMTS和WLAN
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430337
S. D’Amico, M. Matteis, A. Baschirotto, N. Ghittori, A. Vigna, P. Malcovati
{"title":"A 5nV/√Hz-IRN, 78dB-gain-range, 78dB-DR multi-standard baseband chain for Bluetooth, UMTS and WLAN","authors":"S. D’Amico, M. Matteis, A. Baschirotto, N. Ghittori, A. Vigna, P. Malcovati","doi":"10.1109/ESSCIRC.2007.4430337","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430337","url":null,"abstract":"An analog baseband chain for a multistandard (Bluetooth, WCDMA/UMTS, and WLAN) reconfigurable receiver in a 0.25 mum CMOS uses 1.65 mm . The structure is composed by an open-loop programmable-gain amplifier (PGA1), an active-Gm-RC low-pass filter (LPF), and a closed loop programmable-gain amplifier (PGA2). The chain gain can be programmed in the range -10divide68dB, while the input-referred noise (IRN) is 5nV/radicHz. In terms of linearity, the device features an in-band output referred intermodulation intercept point (OIP3) of 21dBm in UMTS mode, and a 1dB compression point of 1.3 dBm in WLAN mode. A dynamic range (DR) larger than 78 dB is achieved for a 1% total harmonic distortion (THD). The current consumption is minimized and adjusted for the different operation conditions, down to 11 mA for the full chain.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129251758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction 栅极偏置电路的SCCMOS功率开关实现最大的泄漏减少
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430303
A. Valentian, E. Beigné
{"title":"Gate bias circuit for an SCCMOS power switch achieving maximum leakage reduction","authors":"A. Valentian, E. Beigné","doi":"10.1109/ESSCIRC.2007.4430303","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430303","url":null,"abstract":"Power switch transistors are very effective in cutting leakage currents of digital circuits in standby mode. Moreover, among the existing power switch transistors, SCCMOS is the most suited to a low-VDD environment since it uses a Iow-VTH transistor. This power switch type achieves good leakage reduction results, provided that an optimal voltage is applied on its gate in order to maximize the leakage gain. This optimal voltage value, depending on the operating conditions (process, voltage, temperature), cannot be determined at the design level. We have therefore designed and fabricated a polarization circuit that automatically finds the optimal bias voltage whatever the environment conditions. This circuit, realized in STMicroelectronics bulk 65 nm technology, achieves more than two decades leakage current reduction at the power switch level, for a power dissipation overhead of 45 nW at ambient temperature.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116127612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Variation tolerant high resolution and low latency time-to-digital converter 可变容错高分辨率和低延迟时间-数字转换器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430278
S. Henzler, S. Koeppe, Dominik Lorenz, W. Kamp, Ronald Kuenemund, D. Schmitt-Landsiedel
{"title":"Variation tolerant high resolution and low latency time-to-digital converter","authors":"S. Henzler, S. Koeppe, Dominik Lorenz, W. Kamp, Ronald Kuenemund, D. Schmitt-Landsiedel","doi":"10.1109/ESSCIRC.2007.4430278","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430278","url":null,"abstract":"A high resolution time-to-digital converter (TDC) with low latency and low deadtime is proposed. A coarse time quantization derived from a differential inverter delay line is locally interpolated with passive voltage dividers. The high resolution TDC is monotonic by construction which makes the concept very robust against process variations. The feasibility is demonstrated with an 8-bit TDC with a resolution of 0.25 inverter delays in a 90 nm low power CMOS technology. The resolution limits imposed by clock uncertainty and local variations are derived theoretically.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116328423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Millimeter-wave amplifiers in 65-nm CMOS 65纳米CMOS毫米波放大器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430298
M. Varonen, M. Kärkkäinen, K. Halonen
{"title":"Millimeter-wave amplifiers in 65-nm CMOS","authors":"M. Varonen, M. Kärkkäinen, K. Halonen","doi":"10.1109/ESSCIRC.2007.4430298","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430298","url":null,"abstract":"We report 40 GHz and 60 GHz amplifiers in 65-nm CMOS achieving state-of-the-art performance. Simulations are verified with on-wafer measurement results. The 40-GHz amplifier exhibits 14.3 dB of gain at 42 GHz and better than 10 dB between 38 to 54 GHz with a compact chip area of 0.286 mm2. The measured noise figure is 6 dB at 50 GHz. The 1-dB output compression point is at +6-dBm power level using a 1.2 V supply. The 60-GHz amplifier achieves better than 11 dB of small-signal gain from 45 to 65 GHz. The measured noise figure is 5.6 dB at 60 GHz and below 6 dB from 55 to 65 GHz. The AM/AM and AM/PM characteristics of the 60-GHz amplifier chip were extracted from the large-signal S-parameter measurement results. The saturated output power is +7 dBm at 60 GHz using a 1.2 V supply. The size of the 60-GHz amplifier is 0.87 mm times 0.70 mm.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126208192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A multistandard Σ-Δ fractional-N frequency synthesizer for 802.11a/b/g WLAN 用于802.11a/b/g WLAN的多标准Σ-Δ分数n频率合成器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430346
A. Bonfanti, C. Samori, A. Lacaita
{"title":"A multistandard Σ-Δ fractional-N frequency synthesizer for 802.11a/b/g WLAN","authors":"A. Bonfanti, C. Samori, A. Lacaita","doi":"10.1109/ESSCIRC.2007.4430346","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430346","url":null,"abstract":"A multistandard WLAN fractional-N frequency synthesizer is implemented in 0.13-mum CMOS. The PLL is able to generate carrier frequency for 802.11a/b/g and Hiper- LAN2 standards. Given the wide tuning range required, the VCO adopts a switched tuning LC tank together with an Adaptive Frequency Calibration (AFC) technique. Measured integral phase noise is less than 3deg rms and the 40-MHz reference spurs are below -40 dBc. Lock time is less than 200 musec. The power consumption is about 50 mW from a 1.2- V supply.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131386598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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