A multistandard Σ-Δ fractional-N frequency synthesizer for 802.11a/b/g WLAN

A. Bonfanti, C. Samori, A. Lacaita
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引用次数: 7

Abstract

A multistandard WLAN fractional-N frequency synthesizer is implemented in 0.13-mum CMOS. The PLL is able to generate carrier frequency for 802.11a/b/g and Hiper- LAN2 standards. Given the wide tuning range required, the VCO adopts a switched tuning LC tank together with an Adaptive Frequency Calibration (AFC) technique. Measured integral phase noise is less than 3deg rms and the 40-MHz reference spurs are below -40 dBc. Lock time is less than 200 musec. The power consumption is about 50 mW from a 1.2- V supply.
用于802.11a/b/g WLAN的多标准Σ-Δ分数n频率合成器
在0.13 μ m CMOS中实现了一个多标准WLAN分数n频率合成器。锁相环能够生成802.11a/b/g和hyper - LAN2标准的载波频率。考虑到所需的宽调谐范围,VCO采用开关调谐LC槽以及自适应频率校准(AFC)技术。测量的积分相位噪声小于3度,40-MHz参考杂散低于-40 dBc。锁时间少于200个博物馆。1.2 V电源的功耗约为50兆瓦。
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