A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme

Abstract

A 8-read, 8-write port, 64-Kbit, 32-bit word-length SRAM design with multi-bank architecture is reported. Using a 2-stage-pipeline, a multi-stage-sensing scheme and a 2-port SRAM cell, high speed and high stability access is achieved simultaneously. The fabricated test chip in 90-nm CMOS technology features 1.2 GHz maximum clock frequency, 0.91 mm Si-area, 0.6 Tbps random-access bandwidth, and 123 mW power dissipation at 1.2 GHz. In comparison with a previously reported 16-port SRAM a bit-area reduction by an order of magnitude is achieved.