K. Johguchi, Y. Mukuda, S. Izumi, H. Mattausch, T. Koide
{"title":"一个0.6 tbps, 16端口SRAM设计，具有2级管道和多级传感方案","authors":"K. Johguchi, Y. Mukuda, S. Izumi, H. Mattausch, T. Koide","doi":"10.1109/ESSCIRC.2007.4430308","DOIUrl":null,"url":null,"abstract":"A 8-read, 8-write port, 64-Kbit, 32-bit word-length SRAM design with multi-bank architecture is reported. Using a 2-stage-pipeline, a multi-stage-sensing scheme and a 2-port SRAM cell, high speed and high stability access is achieved simultaneously. The fabricated test chip in 90-nm CMOS technology features 1.2 GHz maximum clock frequency, 0.91 mm Si-area, 0.6 Tbps random-access bandwidth, and 123 mW power dissipation at 1.2 GHz. In comparison with a previously reported 16-port SRAM a bit-area reduction by an order of magnitude is achieved.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme\",\"authors\":\"K. Johguchi, Y. Mukuda, S. Izumi, H. Mattausch, T. Koide\",\"doi\":\"10.1109/ESSCIRC.2007.4430308\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 8-read, 8-write port, 64-Kbit, 32-bit word-length SRAM design with multi-bank architecture is reported. Using a 2-stage-pipeline, a multi-stage-sensing scheme and a 2-port SRAM cell, high speed and high stability access is achieved simultaneously. The fabricated test chip in 90-nm CMOS technology features 1.2 GHz maximum clock frequency, 0.91 mm Si-area, 0.6 Tbps random-access bandwidth, and 123 mW power dissipation at 1.2 GHz. In comparison with a previously reported 16-port SRAM a bit-area reduction by an order of magnitude is achieved.\",\"PeriodicalId\":121828,\"journal\":{\"name\":\"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference\",\"volume\":\"62 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2007.4430308\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2007.4430308","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 0.6-Tbps, 16-port SRAM design with 2-stage- pipeline and multi-stage-sensing scheme
A 8-read, 8-write port, 64-Kbit, 32-bit word-length SRAM design with multi-bank architecture is reported. Using a 2-stage-pipeline, a multi-stage-sensing scheme and a 2-port SRAM cell, high speed and high stability access is achieved simultaneously. The fabricated test chip in 90-nm CMOS technology features 1.2 GHz maximum clock frequency, 0.91 mm Si-area, 0.6 Tbps random-access bandwidth, and 123 mW power dissipation at 1.2 GHz. In comparison with a previously reported 16-port SRAM a bit-area reduction by an order of magnitude is achieved.
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