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ESSCIRC 2007 - 33rd European Solid-State Circuits Conference最新文献

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A 312-MHz CT Δ∑ modulator using a SC feedback DAC with reduced peak current 采用降低峰值电流的SC反馈DAC的312 mhz CT Δ∑调制器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430288
Martin Anderson, Lars Sundström
{"title":"A 312-MHz CT Δ∑ modulator using a SC feedback DAC with reduced peak current","authors":"Martin Anderson, Lars Sundström","doi":"10.1109/ESSCIRC.2007.4430288","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430288","url":null,"abstract":"This paper presents a second order continuous-time delta-sigma ADC based on a new feedback DAC technique with the low clock jitter sensitivity of the SC (switched-capacitor) technique and the low peak currents of the SI (switched current) technique. The delta-sigma ADC has been implemented in a 90 nm (1.2 V) RF-CMOS process. It measures 66.4 dB maximum SNR over 1.92 MHz bandwidth with a 312 MHz clock while consuming 5mW. Simulations show a high level of clock pulse width suppression and the measured circuit performance is in good agreement with simulations.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116267237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic 一种鲁棒、输入电压自适应、低能耗的亚阈值逻辑变换器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430306
Hui Shao, C. Tsui
{"title":"A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic","authors":"Hui Shao, C. Tsui","doi":"10.1109/ESSCIRC.2007.4430306","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430306","url":null,"abstract":"A new level converter (LC) is proposed for logic voltage shifting between sub-threshold voltage to normal high voltage. By employing 2 PMOS diodes, the LC shows good operation robustness with sub-threshold logic input. The switching delay of the proposed LC can adapt with the input logic voltage which is more suitable for power aware systems. With a simpler circuit structure, the energy consumption of the LC is smaller than that of the existing sub-threshold LC. Simulation results demonstrate the performance improvement and energy reduction of the proposed LC. Test chip was fabricated using 0.18 mum CMOS process. Measurement results show that our proposed LC can operate correctly with an input at as low as 127 mV and an output voltage at 1.8V.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128773387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 67
Designing analog and RF circuits for ultra-low supply voltages 设计超低电源电压的模拟和射频电路
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430882
P. Kinget
{"title":"Designing analog and RF circuits for ultra-low supply voltages","authors":"P. Kinget","doi":"10.1109/ESSDERC.2007.4430882","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430882","url":null,"abstract":"This paper investigates the challenges and opportunities of designing analog and RF integrated circuits to operate from ultra-low supply voltages. Solutions ranging from exploiting the 4 terminals of a MOS device or the threshold voltage dependence on length, to the use of circuit topologies that require only stacks of two devices are discussed. The realization of full analog and RF system functions operating from ultra-low voltages is demonstrated and the enabling architecture modifications are introduced. The techniques and results presented in this paper aim to enable ultra-low voltage analog and RF circuits both in the context of relatively large threshold voltages, e.g., |VT|=VDD, as well as lower threshold voltages.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124633094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS 90nm CMOS无电感预标器60ghz锁相环
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430344
H. Hoshino, R. Tachibana, T. Mitomo, N. Ono, Y. Yoshihara, R. Fujimoto
{"title":"A 60-GHz phase-locked loop with inductor-less prescaler in 90-nm CMOS","authors":"H. Hoshino, R. Tachibana, T. Mitomo, N. Ono, Y. Yoshihara, R. Fujimoto","doi":"10.1109/ESSCIRC.2007.4430344","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430344","url":null,"abstract":"A 60-GHz phase-locked loop (PLL) with inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80 x 40 mum2. The active area of the PLL is 0.6 x 0.6 mm2.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129114019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 43
A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS 90nm CMOS 64GHz 6.5 dB NF 15.5 dB增益LNA
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430316
S. Pellerano, Y. Palaskas, K. Soumyanath
{"title":"A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS","authors":"S. Pellerano, Y. Palaskas, K. Soumyanath","doi":"10.1109/ESSCIRC.2007.4430316","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430316","url":null,"abstract":"This paper presents an integrated LNA for mm-wave applications implemented in 90 nm CMOS technology. Modeling methodology based solely on electromagnetic simulations, RC parasitic extraction and device measurements up to 20 GHz allows for \"correct-by-construction\" design at mm-wave frequency and first-pass silicon success. The dual-stage cascode LNA has a peak gain of 15.5 dB at 64 GHz with an NF of 6.5 dB, while drawing 26 mA per stage from 1.65 V. Output P1dB is 3.8 dBm. At VDD = 1.26 V, each stage draws 19 mA, with a peak gain and a NF of 13.5 dB and 6.7 dB respectively. To the authors' knowledge, this is the lowest measured NF at mm-wave frequencies reported so far in CMOS. Measured results are in excellent agreement with simulations. A custom set-up for mm- wave NF measurement is also extensively described in the paper.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125584595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution 半VDD时钟摆动触发器，减少争用，在时钟分配中节省高达60%的电力
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430277
D. Levacq, M. Yazid, H. Kawaguchi, M. Takamiya, T. Sakurai
{"title":"Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution","authors":"D. Levacq, M. Yazid, H. Kawaguchi, M. Takamiya, T. Sakurai","doi":"10.1109/ESSCIRC.2007.4430277","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430277","url":null,"abstract":"A new low clock swing flip-flop (F/F) is proposed. The existing low clock-swing F/F's consume high power, introduce speed penalty due to contention currents or require large silicon area due to separate well for substrate biasing. By reducing contention currents, our proposal efficiently mitigates those issues. Measurements and simulations are carried out based on a 90 nm CMOS process, demonstrating reductions of active power by 71%, area by 36% and delay by 35% compared to previous proposals. It is shown that the combination of a low- clock swing distribution tree with the new F/F can save up to 60% of the total clock system power.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114378062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Impact of well edge proximity effect on timing 井边接近效应对井时的影响
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1093/ietfec/e91-a.12.3461
T. Kanamoto, Y. Ogasahara, Keiko Natsume, Kenji Yamaguchi, H. Amishiro, Tetsuya Watanabe, M. Hashimoto
{"title":"Impact of well edge proximity effect on timing","authors":"T. Kanamoto, Y. Ogasahara, Keiko Natsume, Kenji Yamaguchi, H. Amishiro, Tetsuya Watanabe, M. Hashimoto","doi":"10.1093/ietfec/e91-a.12.3461","DOIUrl":"https://doi.org/10.1093/ietfec/e91-a.12.3461","url":null,"abstract":"This paper studies impact of the well edge proximity effect on digital circuit delay, based on model parameters extracted from test structures in an industrial 65 nm wafer process. The experimental results show that up to 10% of delay increase arises by the well edge proximity effect in the 65 nm technology, and it depends on interconnect length. Furthermore, due to asymmetric increase in pMOS and nMOS threshold voltages, delay may decrease in spite of the threshold voltage increase. From these results, we conclude that considering WPE is indispensable to cell characterization in the 65 nm technology.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133625608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Analog circuits for sensors 传感器模拟电路
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSDERC.2007.4430888
B. Hosticka
{"title":"Analog circuits for sensors","authors":"B. Hosticka","doi":"10.1109/ESSDERC.2007.4430888","DOIUrl":"https://doi.org/10.1109/ESSDERC.2007.4430888","url":null,"abstract":"This contribution is devoted to CMOS analog circuit design for integrated sensor systems. While today complex sensor signal processing tends to be implemented in digital domain, analog circuits still play a crucial role in sensor signal acquisition due to analog nature of sensory signals. Though sensor front-ends frequently employ analog circuits, e.g. for sensor signal conditioning and conversion, generation of bias and reference voltages and currents, and system interfacing, the most important circuit here - for both, on- and off-chip sensors - is the sensor readout, since it directly interfaces the sensor. At the beginning we review how the key sensor system specifications affect the system and circuit design. A particular attention will be paid to the noise, because it has a great influence on one of the most important parameters of sensor systems, namely the smallest resolvable input signal. On the other hand, it is by far the most difficult parameter to improve upon thus making low-noise circuit design mandatory. For this reason, noise reduction techniques are also of high importance. The contribution will conclude by addressing circuit design issues specific to sensor systems, such as correction of sensor nonidealities, calibration, and testing.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130367960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Low power UWB pulse radio transceiver front-end 低功率UWB脉冲无线电收发前端
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430263
M. Anis, R. Tielert
{"title":"Low power UWB pulse radio transceiver front-end","authors":"M. Anis, R. Tielert","doi":"10.1109/ESSCIRC.2007.4430263","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430263","url":null,"abstract":"In this paper, we propose a low power architecture to extract UWB pulse radio signals from noise level in the presence of narrow band interfering channels. The receiver consists of many narrow band-pass filters, which extract energy either from transmitted UWB signal, interfering channels or noise. Transmitted UWB data can be extracted by statistical correlation of multiple band-pass filter outputs. Super-regenerative receivers, tuned within UWB spectrum, act as band-pass filters. Summer and comparator perform statistical correlation. The test structure of transceiver has been implemented on 0.18 mum CMOS technology, active area of 3.15 mm2, and data exchange rate of 8 Mbits/s with power consumption of 2.6 mw at 1.5 V","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121976351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A CMOS RF front-end with on-chip antenna for V-band broadband wireless communications 用于v波段宽带无线通信的带有片上天线的CMOS射频前端
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430266
Chao-Shiun Wang, Juin-Wei Huang, Shon-Hang Wen, S. Yeh, Chorng-Kuang Wang
{"title":"A CMOS RF front-end with on-chip antenna for V-band broadband wireless communications","authors":"Chao-Shiun Wang, Juin-Wei Huang, Shon-Hang Wen, S. Yeh, Chorng-Kuang Wang","doi":"10.1109/ESSCIRC.2007.4430266","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430266","url":null,"abstract":"This paper presents a V-band receiver front-end for broadband wireless applications. This design consists of an on- chip antenna, a low noise amplifier and a down-conversion mixer with a built-in voltage controlled oscillator as the local oscillator signal. The CPW-fed folded-slot antenna structure was adopted in this work to optimize input impedance matching for the LNA. The measured power gain and input P1dB of the proposed V-band LNA are 18 dB and -17.5 dBm, respectively. The measured isotropic conversion gain at 50 GHz is 23.4 dB. The total V-band RF front-end receiver dissipates 36.6 mW with a 1.2 V supply voltage. The receiver front-end with the on-chip antenna is implemented in a standard 0.13 mum RF CMOS technology without post processing.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121517103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
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