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ESSCIRC 2007 - 33rd European Solid-State Circuits Conference最新文献

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A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier 一个CMOS 100 MHz至6 GHz软件定义无线电模拟前端集成前置功率放大器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430336
M. Ingels, C. Soens, J. Craninckx, V. Giannini, T. Kim, B. Debaillie, M. Libois, M. Goffioul, J. V. Driessche
{"title":"A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier","authors":"M. Ingels, C. Soens, J. Craninckx, V. Giannini, T. Kim, B. Debaillie, M. Libois, M. Goffioul, J. V. Driessche","doi":"10.1109/ESSCIRC.2007.4430336","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430336","url":null,"abstract":"A Software-Defined Radio (SDR) analog front-end is presented that provides extensive programmability of LO generator, LNA, mixers, baseband filters and PPA, supporting various wireless communication standards while guaranteeing a near-optimal power/performance trade-off at any time. The circuit is integrated in a 0.13 mum CMOS technology with 1.2 V supply voltage. This transceiver covers the frequency range from 100 MHz up to 6 GHz by exploiting a flexible zero-IF architecture. The receive path achieves a Noise Figure of 4.8 dB at 174 MHz and 6 dB at 2.4 GHz. For a WLAN OFDM 64 QAM output, the transmitter achieves an EVM better than -29 dB for -0.5 dBm output power at 2.4 GHz and -3.1 dBm output power at 4.9 GHz.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123585915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS 基于0.18 μm CMOS的宽采集范围的1.4 psec抖动2.5 gb /s CDR
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430357
M. Raja, D. Yan, A. Ajjikuttira
{"title":"A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS","authors":"M. Raja, D. Yan, A. Ajjikuttira","doi":"10.1109/ESSCIRC.2007.4430357","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430357","url":null,"abstract":"A fully differential CDR circuit realized in 0.18-mum CMOS technology targeted for the ONU in GPON applications at 2.5 Gb/s is presented. The CDR demonstrates very low RMS jitter of 1.4 psec, along with a acquisition range of 220 MHz employing a simple PLL architecture without a need for any frequency acquisition aid or external reference. The LC VCO employs complementary varactor structure for differential tuning enabling the CDR to function with noisy power supplies. The CDR performs well even when there is no bit transition (Consecutive Identical Digits or CID) for 400 bits in a 211-1 PRBS sequence. The core clock recovery circuit consumes 14.5 mA from 1.8 V power supply. The noise immunity, jitter tolerance and jitter generation of the proposed CDR outperforms a similar CDR with single tuned VCO of same gain and loop bandwidth.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127825980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A configurable High-Side/ low-Side Driver 一个可配置的高侧/低侧驱动
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430292
Michael Wendt, Lenz Thoma, B. Wicht, D. Schmitt-Landsiedel
{"title":"A configurable High-Side/ low-Side Driver","authors":"Michael Wendt, Lenz Thoma, B. Wicht, D. Schmitt-Landsiedel","doi":"10.1109/ESSCIRC.2007.4430292","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430292","url":null,"abstract":"A configurable high-side/low-side driver (HSD/LSD) is presented. The operating mode of this driver depends just upon external connection. The circuit incorporates improved protection circuitry using modified Zener diodes. These diodes are isolated, allowing large negative voltages at source and gate of the switch device. Together with an isolated output stage of the driving circuit, this results in high negative source and gate voltages for the HSD configuration, leading to faster switch-off. This integrated solution with fast and similar HSD/LSD switching times combines the advantages of integrated circuits and the discrete solutions that were used for fast switching HSD up to now, as well as the advantages of both HSD and LSD. Experimental results in a 0.35 mum BiCMOS technology show that the gate can drop as low as -28 V in the high-side configuration. In the low-side configuration, the drain can rise as high as 45 V. In further measurements the configurable driver shows an excellent behaviour both for high-side and low-side in a H-bridge motor driver.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124544963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A I-V 36-pW low-noise adaptive interface IC for portable biomedical applications 一种用于便携式生物医学应用的I-V 36pw低噪声自适应接口IC
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430300
Qiang Li, Kuo Hwi Tan, T. Teo, R. Singh
{"title":"A I-V 36-pW low-noise adaptive interface IC for portable biomedical applications","authors":"Qiang Li, Kuo Hwi Tan, T. Teo, R. Singh","doi":"10.1109/ESSCIRC.2007.4430300","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430300","url":null,"abstract":"This paper presents an adaptive interface ASIC consisting of a low-noise analog front-end and a successive- approximation ADC. The entire analog signal processing chain is fully-differential for better immunity to common-mode noise and interferences. To make the interface adaptive to different biopotential signals, the bandwidth and gain of the analog front-end are configurable. The ADC is designed for rail-to- rail operation and the input full-scale is adjustable so that the resolution requirement can be relaxed. Fabricated in 0.18-mum CMOS, 95-nV/radicHz input-referred noise density and more than 100-dB CMRR are obtained. Operating in 10-bit mode, the ADC exhibits -1/+0.3-LSB DNL and -1.3/+0.8-LSB INL for 1-V rail-to-rail input. The whole interface IC consumes 36 muW from a single 1-V supply, making it suitable for a wide range of low-voltage and low-power biomedical applications.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126305727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement 选择性更换触发器提高嵌入式低功耗微处理器内核的性能
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430305
T. Baumann, J. Berthold, T. Niedermeier, T. Schoenauer, J. Dienstuhl, D. Schmitt-Landsiedel, C. Pacha
{"title":"Performance improvement of embedded low-power microprocessor cores by selective flip flop replacement","authors":"T. Baumann, J. Berthold, T. Niedermeier, T. Schoenauer, J. Dienstuhl, D. Schmitt-Landsiedel, C. Pacha","doi":"10.1109/ESSCIRC.2007.4430305","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430305","url":null,"abstract":"Performance improvement of an ARM926 microprocessor core by selective replacement of standard master-slave flip flops using low-VT flip flops or a novel type of pulsed flip flop (P-FF) is investigated. Different replacement strategies are proposed that are independent of path and pipeline topologies. These strategies are compared to each other concerning performance improvement and costs. For an existing 90 nm CMOS design a 5% speed improvement on design level is achieved at low area overhead of 1%. An experimental verification of the proposed concept using a loop of critical paths shows 12% speed increase at 500 MHz and VDD=1.2 V in a 65 nm CMOS technology.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126751202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Layout options for stability tuning of SRAM cells in multi-gate-FET technologies 多栅极场效应管技术中SRAM单元稳定性调谐的布局选项
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430325
F. Bauer, K. Arnim, C. Pacha, T. Schulz, M. Fulde, A. Nackaerts, M. Jurczak, W. Xiong, K. T. San, C. Cleavelin, K. Schruefer, G. Georgakos, D. Schmitt-Landsiedel
{"title":"Layout options for stability tuning of SRAM cells in multi-gate-FET technologies","authors":"F. Bauer, K. Arnim, C. Pacha, T. Schulz, M. Fulde, A. Nackaerts, M. Jurczak, W. Xiong, K. T. San, C. Cleavelin, K. Schruefer, G. Georgakos, D. Schmitt-Landsiedel","doi":"10.1109/ESSCIRC.2007.4430325","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430325","url":null,"abstract":"We present an investigation of different layout options for multi-gate-FET (MuGFET) SRAM cell design. Measurement results for four different core cell layouts are shown. Two different gate stacks using single mid-gap metal gates and HfSiON/SiON gate oxides were investigated. Static noise margins (SNM) of 210 mV have been measured at IV VDD. Trade-offs for MuGFET SRAM cell design are explored. The impact on cell area and scalability is examined.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131779948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A wide-range duty-independent all-digital multiphase clock generator 宽范围全数字多相时钟发生器
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430276
Hyunsoo Chae, Sangdon Jung, Chulwoo Kim
{"title":"A wide-range duty-independent all-digital multiphase clock generator","authors":"Hyunsoo Chae, Sangdon Jung, Chulwoo Kim","doi":"10.1109/ESSCIRC.2007.4430276","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430276","url":null,"abstract":"A wide-range, input-duty-independent, all-digital, multiphase clock generator is proposed. By using a supply noise filtering block power supply noise effect is reduced. Furthermore, because the proposed clock generator consists of all-digital logic gates, it can be easily migrated to a different process within a short time. The circuit has been fabricated with a 0.18 mum 1P4M CMOS technology and operates over a frequency range from 300 MHz to 1.5 GHz within 5 cycles of reference clock.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134298851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
CMOS image sensors: State-of-the-art and future perspectives CMOS图像传感器:最新的和未来的观点
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430242
A. Theuwissen
{"title":"CMOS image sensors: State-of-the-art and future perspectives","authors":"A. Theuwissen","doi":"10.1109/ESSCIRC.2007.4430242","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430242","url":null,"abstract":"Over the last decade, CMOS image sensor technology made huge progress. Not only the performance of the imagers was drastically improved, but also their commercial success boomed after the introduction of mobile phones with an onboard camera. Many scientists and marketing specialists predicted 15 years ago that CMOS image sensors were going to completely take over from CCD imagers, in the same way as CCD imagers did mid eighties when they took over the imaging business from tubes [1]. Although CMOS has a strong position in imaging today, it did not rule out the business of CCDs. On the other hand, the CMOS-push drastically increased the overall imaging market due to the fact that CMOS image sensors created new application areas and they boosted the performance of CCD imagers as well. This paper describes the state-of-the-art of CMOS image sensors as well as the future perspectives.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"884 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115003030","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 84
Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory 用于混合纳米/ cmos存储器的阻性纳米横条的基本分析
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430310
A. Flocke, T. Noll
{"title":"Fundamental analysis of resistive nano-crossbars for the use in hybrid Nano/CMOS-memory","authors":"A. Flocke, T. Noll","doi":"10.1109/ESSCIRC.2007.4430310","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430310","url":null,"abstract":"As a possible successor for CMOS memory, hysteretic materials organized in crossbar structures are currently being investigated. Here, passive materials are of special importance as they maintain their functionality even when scaled down to the nanometer domain. With their regularity and inherent device density so-called nano-scaled crossbars seem to be very interesting for future components beyond the present scope of the ITRS-CMOS roadmap. But, due to their passive behavior they will not be capable of operating on their own without active devices that restore signal levels. This work investigates the limitations resistive hysteretic crossbars face due to their very nature and what performance CMOS read circuits will have to offer to let hybrid circuits result in a functional new technology.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115546389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 133
The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs 十纳米mosfet输运建模的蒙特卡罗方法
ESSCIRC 2007 - 33rd European Solid-State Circuits Conference Pub Date : 2007-09-01 DOI: 10.1109/ESSCIRC.2007.4430248
E. Sangiorgi, P. Palestri, D. Esseni, C. Fiegna, L. Selmi
{"title":"The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs","authors":"E. Sangiorgi, P. Palestri, D. Esseni, C. Fiegna, L. Selmi","doi":"10.1109/ESSCIRC.2007.4430248","DOIUrl":"https://doi.org/10.1109/ESSCIRC.2007.4430248","url":null,"abstract":"In this paper, we review recent developments of the Monte Carlo approach to the simulation of semi-classical carrier transport in nano-MOSFETs, with particular focus on the inclusion of quantum-mechanical effects in the simulation (using either the Multi-Subband approach or quantum corrections to the electrostatic potential) and on the numerical stability issues related to the coupling of the transport with the Poisson equation. Selected applications are presented, including the analysis of quasi-ballistic transport, the determination of the RF characteristics of deca-nanometric MOSFETs, and the study of non- conventional device structures and channel materials.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116112466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
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