一个CMOS 100 MHz至6 GHz软件定义无线电模拟前端集成前置功率放大器

M. Ingels, C. Soens, J. Craninckx, V. Giannini, T. Kim, B. Debaillie, M. Libois, M. Goffioul, J. V. Driessche
{"title":"一个CMOS 100 MHz至6 GHz软件定义无线电模拟前端集成前置功率放大器","authors":"M. Ingels, C. Soens, J. Craninckx, V. Giannini, T. Kim, B. Debaillie, M. Libois, M. Goffioul, J. V. Driessche","doi":"10.1109/ESSCIRC.2007.4430336","DOIUrl":null,"url":null,"abstract":"A Software-Defined Radio (SDR) analog front-end is presented that provides extensive programmability of LO generator, LNA, mixers, baseband filters and PPA, supporting various wireless communication standards while guaranteeing a near-optimal power/performance trade-off at any time. The circuit is integrated in a 0.13 mum CMOS technology with 1.2 V supply voltage. This transceiver covers the frequency range from 100 MHz up to 6 GHz by exploiting a flexible zero-IF architecture. The receive path achieves a Noise Figure of 4.8 dB at 174 MHz and 6 dB at 2.4 GHz. For a WLAN OFDM 64 QAM output, the transmitter achieves an EVM better than -29 dB for -0.5 dBm output power at 2.4 GHz and -3.1 dBm output power at 4.9 GHz.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"39","resultStr":"{\"title\":\"A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier\",\"authors\":\"M. Ingels, C. Soens, J. Craninckx, V. Giannini, T. Kim, B. Debaillie, M. Libois, M. Goffioul, J. V. Driessche\",\"doi\":\"10.1109/ESSCIRC.2007.4430336\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Software-Defined Radio (SDR) analog front-end is presented that provides extensive programmability of LO generator, LNA, mixers, baseband filters and PPA, supporting various wireless communication standards while guaranteeing a near-optimal power/performance trade-off at any time. The circuit is integrated in a 0.13 mum CMOS technology with 1.2 V supply voltage. This transceiver covers the frequency range from 100 MHz up to 6 GHz by exploiting a flexible zero-IF architecture. The receive path achieves a Noise Figure of 4.8 dB at 174 MHz and 6 dB at 2.4 GHz. For a WLAN OFDM 64 QAM output, the transmitter achieves an EVM better than -29 dB for -0.5 dBm output power at 2.4 GHz and -3.1 dBm output power at 4.9 GHz.\",\"PeriodicalId\":121828,\"journal\":{\"name\":\"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"39\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2007.4430336\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2007.4430336","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 39

摘要

提出了一种软件定义无线电(SDR)模拟前端,它提供了LO发生器、LNA、混频器、基带滤波器和PPA的广泛可编程性,支持各种无线通信标准,同时保证在任何时候都能实现近乎最佳的功率/性能权衡。该电路集成在0.13 μ m CMOS技术和1.2 V电源电压。该收发器采用灵活的零中频架构,覆盖100 MHz至6 GHz的频率范围。接收路径的噪声系数在174mhz时为4.8 dB,在2.4 GHz时为6 dB。对于WLAN OFDM 64 QAM输出,在2.4 GHz和4.9 GHz下,发射器在-0.5 dBm输出功率和-3.1 dBm输出功率下的EVM优于-29 dB。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A CMOS 100 MHz to 6 GHz software defined radio analog front-end with integrated pre-power amplifier
A Software-Defined Radio (SDR) analog front-end is presented that provides extensive programmability of LO generator, LNA, mixers, baseband filters and PPA, supporting various wireless communication standards while guaranteeing a near-optimal power/performance trade-off at any time. The circuit is integrated in a 0.13 mum CMOS technology with 1.2 V supply voltage. This transceiver covers the frequency range from 100 MHz up to 6 GHz by exploiting a flexible zero-IF architecture. The receive path achieves a Noise Figure of 4.8 dB at 174 MHz and 6 dB at 2.4 GHz. For a WLAN OFDM 64 QAM output, the transmitter achieves an EVM better than -29 dB for -0.5 dBm output power at 2.4 GHz and -3.1 dBm output power at 4.9 GHz.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:604180095
Book学术官方微信