Layout options for stability tuning of SRAM cells in multi-gate-FET technologies

Abstract

We present an investigation of different layout options for multi-gate-FET (MuGFET) SRAM cell design. Measurement results for four different core cell layouts are shown. Two different gate stacks using single mid-gap metal gates and HfSiON/SiON gate oxides were investigated. Static noise margins (SNM) of 210 mV have been measured at IV VDD. Trade-offs for MuGFET SRAM cell design are explored. The impact on cell area and scalability is examined.