{"title":"一种鲁棒、输入电压自适应、低能耗的亚阈值逻辑变换器","authors":"Hui Shao, C. Tsui","doi":"10.1109/ESSCIRC.2007.4430306","DOIUrl":null,"url":null,"abstract":"A new level converter (LC) is proposed for logic voltage shifting between sub-threshold voltage to normal high voltage. By employing 2 PMOS diodes, the LC shows good operation robustness with sub-threshold logic input. The switching delay of the proposed LC can adapt with the input logic voltage which is more suitable for power aware systems. With a simpler circuit structure, the energy consumption of the LC is smaller than that of the existing sub-threshold LC. Simulation results demonstrate the performance improvement and energy reduction of the proposed LC. Test chip was fabricated using 0.18 mum CMOS process. Measurement results show that our proposed LC can operate correctly with an input at as low as 127 mV and an output voltage at 1.8V.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"67","resultStr":"{\"title\":\"A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic\",\"authors\":\"Hui Shao, C. Tsui\",\"doi\":\"10.1109/ESSCIRC.2007.4430306\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new level converter (LC) is proposed for logic voltage shifting between sub-threshold voltage to normal high voltage. By employing 2 PMOS diodes, the LC shows good operation robustness with sub-threshold logic input. The switching delay of the proposed LC can adapt with the input logic voltage which is more suitable for power aware systems. With a simpler circuit structure, the energy consumption of the LC is smaller than that of the existing sub-threshold LC. Simulation results demonstrate the performance improvement and energy reduction of the proposed LC. Test chip was fabricated using 0.18 mum CMOS process. Measurement results show that our proposed LC can operate correctly with an input at as low as 127 mV and an output voltage at 1.8V.\",\"PeriodicalId\":121828,\"journal\":{\"name\":\"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"67\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2007.4430306\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2007.4430306","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 67
摘要
提出了一种新的电平变换器(LC),用于在亚阈值电压和正常高压之间进行逻辑电压转换。通过采用两个PMOS二极管,LC具有良好的亚阈值逻辑输入鲁棒性。该电路的开关延时可以随输入逻辑电压的变化而变化,更适合于功率感知系统。电路结构简单,能耗比现有的亚阈值LC小。仿真结果表明,所提出的LC提高了性能,降低了能耗。采用0.18 μ m CMOS工艺制备了测试芯片。测量结果表明,在输入电压低至127 mV,输出电压为1.8V的情况下,LC可以正常工作。
A robust, input voltage adaptive and low energy consumption level converter for sub-threshold logic
A new level converter (LC) is proposed for logic voltage shifting between sub-threshold voltage to normal high voltage. By employing 2 PMOS diodes, the LC shows good operation robustness with sub-threshold logic input. The switching delay of the proposed LC can adapt with the input logic voltage which is more suitable for power aware systems. With a simpler circuit structure, the energy consumption of the LC is smaller than that of the existing sub-threshold LC. Simulation results demonstrate the performance improvement and energy reduction of the proposed LC. Test chip was fabricated using 0.18 mum CMOS process. Measurement results show that our proposed LC can operate correctly with an input at as low as 127 mV and an output voltage at 1.8V.