{"title":"采用降低峰值电流的SC反馈DAC的312 mhz CT Δ∑调制器","authors":"Martin Anderson, Lars Sundström","doi":"10.1109/ESSCIRC.2007.4430288","DOIUrl":null,"url":null,"abstract":"This paper presents a second order continuous-time delta-sigma ADC based on a new feedback DAC technique with the low clock jitter sensitivity of the SC (switched-capacitor) technique and the low peak currents of the SI (switched current) technique. The delta-sigma ADC has been implemented in a 90 nm (1.2 V) RF-CMOS process. It measures 66.4 dB maximum SNR over 1.92 MHz bandwidth with a 312 MHz clock while consuming 5mW. Simulations show a high level of clock pulse width suppression and the measured circuit performance is in good agreement with simulations.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 312-MHz CT Δ∑ modulator using a SC feedback DAC with reduced peak current\",\"authors\":\"Martin Anderson, Lars Sundström\",\"doi\":\"10.1109/ESSCIRC.2007.4430288\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a second order continuous-time delta-sigma ADC based on a new feedback DAC technique with the low clock jitter sensitivity of the SC (switched-capacitor) technique and the low peak currents of the SI (switched current) technique. The delta-sigma ADC has been implemented in a 90 nm (1.2 V) RF-CMOS process. It measures 66.4 dB maximum SNR over 1.92 MHz bandwidth with a 312 MHz clock while consuming 5mW. Simulations show a high level of clock pulse width suppression and the measured circuit performance is in good agreement with simulations.\",\"PeriodicalId\":121828,\"journal\":{\"name\":\"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.2007.4430288\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2007.4430288","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 312-MHz CT Δ∑ modulator using a SC feedback DAC with reduced peak current
This paper presents a second order continuous-time delta-sigma ADC based on a new feedback DAC technique with the low clock jitter sensitivity of the SC (switched-capacitor) technique and the low peak currents of the SI (switched current) technique. The delta-sigma ADC has been implemented in a 90 nm (1.2 V) RF-CMOS process. It measures 66.4 dB maximum SNR over 1.92 MHz bandwidth with a 312 MHz clock while consuming 5mW. Simulations show a high level of clock pulse width suppression and the measured circuit performance is in good agreement with simulations.
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