{"title":"A 64GHz 6.5 dB NF 15.5 dB gain LNA in 90nm CMOS","authors":"S. Pellerano, Y. Palaskas, K. Soumyanath","doi":"10.1109/ESSCIRC.2007.4430316","DOIUrl":null,"url":null,"abstract":"This paper presents an integrated LNA for mm-wave applications implemented in 90 nm CMOS technology. Modeling methodology based solely on electromagnetic simulations, RC parasitic extraction and device measurements up to 20 GHz allows for \"correct-by-construction\" design at mm-wave frequency and first-pass silicon success. The dual-stage cascode LNA has a peak gain of 15.5 dB at 64 GHz with an NF of 6.5 dB, while drawing 26 mA per stage from 1.65 V. Output P1dB is 3.8 dBm. At VDD = 1.26 V, each stage draws 19 mA, with a peak gain and a NF of 13.5 dB and 6.7 dB respectively. To the authors' knowledge, this is the lowest measured NF at mm-wave frequencies reported so far in CMOS. Measured results are in excellent agreement with simulations. A custom set-up for mm- wave NF measurement is also extensively described in the paper.","PeriodicalId":121828,"journal":{"name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.2007.4430316","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 21
Abstract
This paper presents an integrated LNA for mm-wave applications implemented in 90 nm CMOS technology. Modeling methodology based solely on electromagnetic simulations, RC parasitic extraction and device measurements up to 20 GHz allows for "correct-by-construction" design at mm-wave frequency and first-pass silicon success. The dual-stage cascode LNA has a peak gain of 15.5 dB at 64 GHz with an NF of 6.5 dB, while drawing 26 mA per stage from 1.65 V. Output P1dB is 3.8 dBm. At VDD = 1.26 V, each stage draws 19 mA, with a peak gain and a NF of 13.5 dB and 6.7 dB respectively. To the authors' knowledge, this is the lowest measured NF at mm-wave frequencies reported so far in CMOS. Measured results are in excellent agreement with simulations. A custom set-up for mm- wave NF measurement is also extensively described in the paper.