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A Zero-Crossing Detection Circuit for Energy Harvesting 一种能量收集的过零检测电路
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278357
Zhang Zhang, Tang Zechen, Hu Wei, Xie Guangjun, Liu Gang, Cheng Xin
{"title":"A Zero-Crossing Detection Circuit for Energy Harvesting","authors":"Zhang Zhang, Tang Zechen, Hu Wei, Xie Guangjun, Liu Gang, Cheng Xin","doi":"10.1109/ICSICT49897.2020.9278357","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278357","url":null,"abstract":"Synchronized switch harvesting on capacitors (SSHC) circuit can effectively improve the efficiency of piezoelectric energy harvesting circuit. However, its output power and voltage flip efficiency are deeply affected by the accuracy of zero-crossing detection circuit. Based on SSHC circuit using potential comparison method, a piezoelectric energy harvesting circuit composed of piezoelectric element, zero-crossing detection circuit, pulse generation circuit, full-bridge rectifier and load is designed. The zero-crossing detection circuit using sampling resistance method can accurately determines the closing time of switches and improve the accuracy of this circuit. The simulation results show that this circuit can effectively improve the voltage flip efficiency and output power, too. In the case of a load of 100kΩ, the output power of proposed circuit is 368.72μW. Compared with the single-capacitor SSHC circuit using potential comparison method, it is improved by 46.08%.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"45 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74966106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design Of LC Harmonic Notch Filter for Ripple Reduction in Step-Down DC-DC Buck Converter 降压DC-DC降压变换器中LC谐波陷波滤波器的设计
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278270
MinhTri Tran, Y. Kobori, A. Kuwana, Haruo Kobayashi
{"title":"Design Of LC Harmonic Notch Filter for Ripple Reduction in Step-Down DC-DC Buck Converter","authors":"MinhTri Tran, Y. Kobori, A. Kuwana, Haruo Kobayashi","doi":"10.1109/ICSICT49897.2020.9278270","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278270","url":null,"abstract":"This paper proposes the design of an LC harmonic notch filter to improve the output ripple in an inductor type step-down DC-DC buck converter. To examine the overshoot voltage of the converter, the transfer function and its self-loop function of the power stage were analyzed. The LC network was designed at the 180 kHz harmonic frequency and added at the output node of the power stage of the converter. As a result, the ripple was reduced by 3 dB (from -35 dBV to -42 dBV at 180 kHz). The ripple level was kept below 5 mVpp, which is small enough compared to 5 V desired voltage.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"38 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74669061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Unijunction Transistor on Silicon-On-Insulator Substrate 绝缘体上硅衬底单结晶体管
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278352
Yx Chen, J. Liu, K. Xiao, A. Zaslavsky, S. Cristoloveanu, F. Liu, BH. Li, B. Li, J. Wan
{"title":"Unijunction Transistor on Silicon-On-Insulator Substrate","authors":"Yx Chen, J. Liu, K. Xiao, A. Zaslavsky, S. Cristoloveanu, F. Liu, BH. Li, B. Li, J. Wan","doi":"10.1109/ICSICT49897.2020.9278352","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278352","url":null,"abstract":"A unijunction transistor based on fully-depleted silicon-on-insulator substrate is proposed. The device structure is similar to a junction field effect transistor. By conducting the TCAD simulation, we observe sharp switching and large hysteresis in emitter current-emitter voltage curves with the turn-on voltage linearly controlled by the second base voltage. The operation of the device is mainly determined by the emitter-channel PN junction, which is induced by the backgate voltage. The impact of the backgate voltage on the electrical characteristics is analyzed by changes in the channel potential.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"4 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72759889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Pico-second Resolution Sensor of NTV DFF Timing Variation with Cancelling Errors from PVT and RC Delay along Testing Path 一种带PVT和RC延时抵消误差的NTV DFF时序变化皮秒分辨率传感器
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278326
Wen Wang, Shuming Cui, Yinyin Lin
{"title":"A Pico-second Resolution Sensor of NTV DFF Timing Variation with Cancelling Errors from PVT and RC Delay along Testing Path","authors":"Wen Wang, Shuming Cui, Yinyin Lin","doi":"10.1109/ICSICT49897.2020.9278326","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278326","url":null,"abstract":"A novel circuit for testing sequential element setup time and hold time variation at near threshold voltage (NTV) is proposed and verified at 28nm HKMG node. A structure of two-path with configurable delay differentiation enables to cancel testing errors introduced by PVT variations and RC delay along the testing path. Pico-seconds of resolution is achieved. Simulation of setup/hold time is implemented with variable voltage, process corner, temperature and data edge. The results indicate that the scenario of data rising edge has a larger setup&hold time than the scenario of data falling edge at NTV.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"15 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85038662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A low-Power SRAM with charge cycling based read and write assist scheme 一种基于充电循环读写辅助方案的低功耗SRAM
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278282
Hanzun Zhang, S. Jia, Jiancheng Yang, Yuan Wang
{"title":"A low-Power SRAM with charge cycling based read and write assist scheme","authors":"Hanzun Zhang, S. Jia, Jiancheng Yang, Yuan Wang","doi":"10.1109/ICSICT49897.2020.9278282","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278282","url":null,"abstract":"In a SRAM array, the largest power consumer is pre-charging or voltage switching on bit-lines in read or write operations. The paper presents a bit-line charge cycling based read and write assist circuit for static random-access memory. With help of the assist circuit, the BLs charges wasted in conventional design is reused for BLs pre-charging in next period. The proposed array is simulated in SMIC 14nm FinFET process with a supply voltage of 0.8V. Simulation results show that a 23%-43% power reduction is achieved compared with conventional designs.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"27 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85203294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Highly-Sensitive FET-based Sensor via Heterogeneous Selective-Assembling Integration of Porphyrin and Silicon Nanowires 基于卟啉和硅纳米线非均匀选择性组装集成的高灵敏度场效应效应传感器
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278265
Xiaokang Li, Bocheng Yu, Gong Chen, Ming Li
{"title":"Highly-Sensitive FET-based Sensor via Heterogeneous Selective-Assembling Integration of Porphyrin and Silicon Nanowires","authors":"Xiaokang Li, Bocheng Yu, Gong Chen, Ming Li","doi":"10.1109/ICSICT49897.2020.9278265","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278265","url":null,"abstract":"In this paper, we proposed and fabricated a novel heterogeneous porphyrin/silicon nanowire transistor-based sensor using CMOS process technology. With the difference in hydrophobicity of Si3N4 and SiO2, the enrichment of porphyrin molecules on silicon nanowires was achieved, and the device showed highly sensitive photo-sensing even under very low illumination power $(Delta mathrm{V}_{mathrm{t}}=3.32mathrm{V}$ @11.3µW/cm2), great dynamic photo-memory characteristic $(Delta mathrm{V}_{mathrm{t}}=31.3mathrm{V}$ @ programming/erasing time of 10s) and excellent temperature sensing $(Delta mathrm{V}_{mathrm{t}}=13.6mathrm{V}$ @ 90°C temperature range). Those performances make the devices applicable to be used in applications of sensitive and smart non-memory light sensing and reliable temperature sensing.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"35 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82155273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design for Saddle-Fin Device Performance Boosting with Dual Work Function Gate Formation Word Line 双工作功能闸口形成字线的鞍鳍装置性能提升设计
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278242
Xiang Liu, R. Jiang, Ning Li, Hang Yang, Jongsung Jeon, Blacksmith Wu, M. Cao
{"title":"Design for Saddle-Fin Device Performance Boosting with Dual Work Function Gate Formation Word Line","authors":"Xiang Liu, R. Jiang, Ning Li, Hang Yang, Jongsung Jeon, Blacksmith Wu, M. Cao","doi":"10.1109/ICSICT49897.2020.9278242","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278242","url":null,"abstract":"In the past decades, dynamic random access memory(DRAM) has continued to scaling down to obtain higher data storage ability. As for the access transistor, much effort has been dedicated to reduce leakage and obtain sufficient drivability to improve retention time and access speed. However, it become more and more difficult when the technology nodes beyond 20nm. In our work, the saddle fin access transistor with a dual work function word line structure has been investigated with TCAD simulation. An improved performance with suppressed GIDL leakage and enhanced drive current have been obtained. We have analyzed the word line engineering effects on the electric field and band to band tunneling.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"191 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79769418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
28nm 4Mb 1T-1MTJ STT-MRAM Circuits with Ultra-low Power Read Scheme 采用超低功耗读取方案的28nm 4Mb 1T-1MTJ STT-MRAM电路
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278155
S. Zheng, J. Bi, K. Xi, Bo Li
{"title":"28nm 4Mb 1T-1MTJ STT-MRAM Circuits with Ultra-low Power Read Scheme","authors":"S. Zheng, J. Bi, K. Xi, Bo Li","doi":"10.1109/ICSICT49897.2020.9278155","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278155","url":null,"abstract":"4Mb 1T-1MTJ STT-MRAM based on 28nm CMOS process has been designed. To improve reading performance, a novel sense amplifier structure, achieving ultra-low power consumption, has been proposed. The read power consumption is as low as 1pJ/bit. The simulation results of the whole STT-MRAM chip demonstrate good performance.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"12 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85370308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Single Event Transient Pulses Fault Injection Model based on LET for Circuit-Level Simulation 基于LET的单事件暂态脉冲故障注入模型电路级仿真
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278217
Changqin Xu, Yi Liu, Xiaodong Weng, Zhi-Bing Li, Yin-tang Yang
{"title":"Single Event Transient Pulses Fault Injection Model based on LET for Circuit-Level Simulation","authors":"Changqin Xu, Yi Liu, Xiaodong Weng, Zhi-Bing Li, Yin-tang Yang","doi":"10.1109/ICSICT49897.2020.9278217","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278217","url":null,"abstract":"The dependence of 0.13µm NMOS single event transient on linear energy transfer (LET) is studied and integrated into a single event transient (SET) pulses fault injection model. A modified double exponential function with four parameters that are related to LET is used to fit the single event transient pulsed current. By translating into the LET-dependent model, it can predict the charge collection without Technology Computer Aided Design (TCAD) simulation when LET is changed. The SRAM unit is built using the proposed single event transient pulses fault injection model into the sensitive node, proving the practicability and reasonableness of the proposed fault injection model for circuit-level single-event effect (SEE) simulation.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"40 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82653500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Influence of Gate-Drain Underlap Length on Germanium Gate-All-Around Tunneling Field-Effect-Transistors 栅极-漏极搭接长度对锗栅极-全隧道场效应晶体管的影响
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278269
Kai-Xiao Wei, Xiaojin Li, Yabin Sun, Yanling Shi
{"title":"Influence of Gate-Drain Underlap Length on Germanium Gate-All-Around Tunneling Field-Effect-Transistors","authors":"Kai-Xiao Wei, Xiaojin Li, Yabin Sun, Yanling Shi","doi":"10.1109/ICSICT49897.2020.9278269","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278269","url":null,"abstract":"In this paper, the influence of gate-drain underlap length (L<inf>un</inf>) of germanium gate-all-around tunneling field-effect-transistors (Ge-GAA- TFETs) is investigated. Based on the TCAD simulation, the I- V and C- V characteristics of GAA- TFETs with different L<inf>un</inf>are obtained, and the results show that ambipolar current (Iamp) and Cgd considerably decrease with the increase in L<inf>un</inf>, whereas <tex>$C$</tex><inf>gs</inf> is independent on L<inf>un</inf>. Moreover, the method of device circuit co-design is used to evaluate the impact of L<inf>un</inf>on logic performance including propagation delay (tpd) and energy-delay-product (EDP). Compared with no underlap structure, the tpd reduction of 40% @V<inf>DD</inf>= 0.2 V is achieved in both inverter and two-input NAND with 10 nm underlap structure. The EDP reduction up to 67% and 66% at V<inf>DD</inf>= 0.2 V are obtained in the inverter and two-input NAND, respectively. Therefore, we can conclude that the longer L<inf>un</inf>benefits in mitigating both tpd and EDP.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"39 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80476167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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