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2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)最新文献

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Improved Device Performance of MoTe2 nanoribbon Transistors with Solution-processed Ternary HfAlOx High-k Dielectric 溶液处理三元HfAlOx高k介电介质改善MoTe2纳米带晶体管器件性能
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278339
Yuan Liu, Zijian Xie, Li Yang, Xiaokun Wen, Wenyu Lei, Haixin Chang, Wenfeng Zhang
{"title":"Improved Device Performance of MoTe2 nanoribbon Transistors with Solution-processed Ternary HfAlOx High-k Dielectric","authors":"Yuan Liu, Zijian Xie, Li Yang, Xiaokun Wen, Wenyu Lei, Haixin Chang, Wenfeng Zhang","doi":"10.1109/ICSICT49897.2020.9278339","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278339","url":null,"abstract":"In this paper, we focus on improving MoTe<inf>2</inf> nanoribbon MOSFETs device performance, with solution-processed HfAlOx high-k dielectric film compared with SiO<inf>2</inf>. First, 2H-MoTe<inf>2</inf> nanoribbons with high purity and quality were synthesized by CVD process. Then, solution-processed synthesis of HfAlOx thin film was systematically investigated. HfAlOx thin film obtained with 0.3M precursor concentration, annealing at 400°C in mixed gas of N<inf>2</inf>(95%) + H2(5%) showed low leakage current density and high k value. Finally, improved device performance of MoTe<inf>2</inf> nanoribbon transistors with mobility ~9.35 cm<sup>2</sup>V<sup>−1</sup>s<sup>−1</sup>, I<inf>on</inf>/I<inf>off</inf> ratio ~1.85×l0<sup>5</sup>, and the threshold voltage ~ -3.52V were demonstrated.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"6 8","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91430479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evaluation of Cu/Graphene Integration Schemes for Its Application on CMOS BEOL Interconnect 铜/石墨烯集成方案在CMOS BEOL互连中的应用评估
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278193
Xiaoxu Kang, Zhengxi Cheng, Qingyun Zuo, Weijun Wang, Ruoxi Shen, Xiaolan Zhong, Zhangfa Chen, Shoumian Chen, Yuhang Zhao
{"title":"Evaluation of Cu/Graphene Integration Schemes for Its Application on CMOS BEOL Interconnect","authors":"Xiaoxu Kang, Zhengxi Cheng, Qingyun Zuo, Weijun Wang, Ruoxi Shen, Xiaolan Zhong, Zhangfa Chen, Shoumian Chen, Yuhang Zhao","doi":"10.1109/ICSICT49897.2020.9278193","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278193","url":null,"abstract":"With CMOS technology feature size continually scaling down, EM reliability issue of Cu interconnect is becoming more and more severe. As a 2D material, Graphene can sustain much higher current density, which may have potential application value to CMOS BEOL interconnect. And introduction of Graphene as capping layer on Cu metal line will be a much more effective way to improve the Cu interconnect EM performance. In this work, different Cu/Graphene integration schemes were implemented and evaluated based on 200mm Cu BEOL, including transfer based scheme and self-aligned scheme, and advantages and drawbacks of these schemes were analyzed. Further work is still ongoing for optimizing the integration scheme and realizing process integration of the Cu/Graphene interconnect on 200mm Cu BEOL.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"21 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80920621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Ka-Band High-Gain and Wideband mmW Down-Conversion Mixer for 5G Communication Applications 一种用于5G通信应用的ka波段高增益宽带毫米波下变频混频器
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278246
Rongsheng Bao, Shengyu Rao, C. Shi, Jinghong Chen, Guangsheng Chen, Runxi Zhang
{"title":"A Ka-Band High-Gain and Wideband mmW Down-Conversion Mixer for 5G Communication Applications","authors":"Rongsheng Bao, Shengyu Rao, C. Shi, Jinghong Chen, Guangsheng Chen, Runxi Zhang","doi":"10.1109/ICSICT49897.2020.9278246","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278246","url":null,"abstract":"This paper implements a high-gain and wideband CMOS mmW down-conversion mixer for 5G communication applications. A parallel inductor is exploited to eliminate the parasitic capacitance between the transconductance transistors and the switching transistors. The dynamic current injection (DCI) method based on the cross-coupled transistors is proposed to realize the negative resistance to cancel the loss resistance, which is introduced by the parallel inductor, and then the gain is improved while the noise is reduced. A resonating peak control (RPC) technology based on the passive transformer is utilized to improve bandwidth. The chip is designed using 40-nm CMOS process and the simulated peak conversion gain (CG) is 16.78 dB at 26 GHz. The 3 dB bandwidth is from 24 to 30 GHz. The minimum noise figure (NF) is 9.65 dB and the input P1dB is -11 dBm. The DC power consumption is 16 mW.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"5 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84669970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Wireless data and power transfer in 3-D integration 三维集成中的无线数据和能量传输
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278336
Xiaohang Wang, Yong Shi, Libo Oian
{"title":"Wireless data and power transfer in 3-D integration","authors":"Xiaohang Wang, Yong Shi, Libo Oian","doi":"10.1109/ICSICT49897.2020.9278336","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278336","url":null,"abstract":"This paper proposes a new scheme for achieving power and data simultaneous transmission. Data is transferred through parasitic capacitances between the coupling coils at a high frequency, while power is transferred through inductive coupling coils at a low frequency. Firstly, topology structure of the proposed concurrent data and power transfer links is introduced. Secondly, the capability of data transfer and the interference of power on data transfer are analyzed. Simulation results show the system has excellent SNR performance, offset tolerance performance and small time delay. Finally, a 1.26W, 200Kbps simulation model is achieved.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"112 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88802510","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS Readout Circuit with Low Detection Limit and High Linearity for Perovskite-based Direct X-ray Detector 用于钙钛矿直接x射线探测器的低检测限高线性CMOS读出电路
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278370
Hao Li, Guangda Niu, Zheng Nie, Jiang Tang, Dongsheng Liu
{"title":"A CMOS Readout Circuit with Low Detection Limit and High Linearity for Perovskite-based Direct X-ray Detector","authors":"Hao Li, Guangda Niu, Zheng Nie, Jiang Tang, Dongsheng Liu","doi":"10.1109/ICSICT49897.2020.9278370","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278370","url":null,"abstract":"A CMOS readout circuit with low detection limit and high linearity for perovskite-based direct X-ray detector is proposed in this paper. We model the input signal of perovskite as a current source and the readout circuit includes a 64 ×64 four-transistor active pixel sensor (4T APS) pixel array and an amplification circuit with 1.2× voltage magnification. The pixel size is 20µm×20µm and a 15.5fF MIM capacitor is employed to convert the input current into voltage during the integration time. Correlated double sample (CDS) structure is designed to decrease the random noise. The circuit is designed with SMIC 180nm Mixed Signal process. The current range of perovskite is 0-2.25pA and the corresponding output voltage is -442.5mV-864.7mV within 10ms typical integration time. The linearity of signal exceeds 99%.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"13 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84811145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Enhanced Data Cache with In-Cache Processing Units for Convolutional Neural Network Accelerators 卷积神经网络加速器的增强型数据缓存与缓存内处理单元
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278154
Yuchao Zhou, Mai Lei, Yong-Liang Zhang, Quan Zhang, Jun Han
{"title":"An Enhanced Data Cache with In-Cache Processing Units for Convolutional Neural Network Accelerators","authors":"Yuchao Zhou, Mai Lei, Yong-Liang Zhang, Quan Zhang, Jun Han","doi":"10.1109/ICSICT49897.2020.9278154","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278154","url":null,"abstract":"Convolutional neural network algorithms rely on large quantities of data to extract hidden information. In order to achieve good performance, a CNN accelerator should be able to easily access a wide range of memory space. However, on-chip memory has limited capacity, and needs to be manually managed by the accelerator controller. Besides, accessing off-chip memory like a DRAM array needs a physical address, which is not calculated until a memory access request arrives at a memory access control unit. Managing those issues manually complicates CNN accelerator design. Therefore, we propose a data cache enhanced with in-cache processing units, which processes segment address in parallel with data, and exploits data locality in an automatic manner. Overheads such as physical address translation, quantization, and ReLU, are offloaded from the accelerator controller.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"74 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79668812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Enhanced Heuristic Layer Assignment Method in Global Routing 一种改进的启发式全局路由层分配方法
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278166
Jinwei Chen, Zhixiong Di, Jia-Jie Chen, Quanyuan Feng, Jiang-Yi Shi
{"title":"An Enhanced Heuristic Layer Assignment Method in Global Routing","authors":"Jinwei Chen, Zhixiong Di, Jia-Jie Chen, Quanyuan Feng, Jiang-Yi Shi","doi":"10.1109/ICSICT49897.2020.9278166","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278166","url":null,"abstract":"Layer assignment, which is a part of global routing, aims to assign the flat nets to 3D distribution and decrease the via count without violating edge or via constraint. Negotiation-based method is used to obtain good result but bring too much time complexity, this work presents a net partition technology to reduce the problem complexity, and develops enhanced heuristic methods of effective layer shifting and rip-up procedure which could control the via count without multiple iteration process. Experimental results show that this method could bring inspiring improvement than LAVA.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"55 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90917567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs 3nm栅极全能纳米片场效应管的设计技术协同优化
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278197
Meng Wang, Yabin Sun, Xiaojin Li, Yanling Shi, ShaoJian Hu, Enming Shang, Shoumian Chen
{"title":"Design Technology Co-Optimization for 3 nm Gate-All-Around Nanosheet FETs","authors":"Meng Wang, Yabin Sun, Xiaojin Li, Yanling Shi, ShaoJian Hu, Enming Shang, Shoumian Chen","doi":"10.1109/ICSICT49897.2020.9278197","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278197","url":null,"abstract":"In this work, an improved TCAD based Design Technology Co-Optimization (DTCO) is proposed for gate-all-around (GAA) Nanosheet FET (NSFET) at 3 nm technology node. Based on conventional DTCO, only an additional procedure is introduced to extract the SPICE model, while the huge computational expense in the TCAD simulation is saved. Compared to the 5 nm technology node, the performance of ring oscillator (RO) in the optimized 3 nm technology node increases by 30%, while the power decreases by 56%. Besides, dual-k spacer design for NSFETs at the device and circuit levels are also investigated.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"31 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78406507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Net-distribution-based Routability Optimization In Global Placement 全局布局中基于网络分布的可达性优化
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278264
Dingcheng Li, Cong Li, Likang Tao, Y. Zhuang, Gengjie Chen
{"title":"Net-distribution-based Routability Optimization In Global Placement","authors":"Dingcheng Li, Cong Li, Likang Tao, Y. Zhuang, Gengjie Chen","doi":"10.1109/ICSICT49897.2020.9278264","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278264","url":null,"abstract":"The placement only considering the wirelength may cause a lot of troubles in routing later. So routability is an important measure of placement results. In this paper, we propose algorithms for routability optimization including net-distribution-based cell inflation, inflation ratio adjustment and net replacement. Compared with normal cell inflation, our placer are more effective on the congestion caused by global nets and more robust. On ICCAD 2012 [3] benchmarks, our placer obtains better solutions than other placers.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"9 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75451291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design of High-Performance Phase-Locked Loop Using Hybrid Dual-Path Loop Architecture: an Overview (Invited Paper) 基于混合双路环结构的高性能锁相环设计综述(特邀论文)
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278255
Zhao Zhang, N. Wu
{"title":"Design of High-Performance Phase-Locked Loop Using Hybrid Dual-Path Loop Architecture: an Overview (Invited Paper)","authors":"Zhao Zhang, N. Wu","doi":"10.1109/ICSICT49897.2020.9278255","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278255","url":null,"abstract":"The performance requirements of phase-locked loops (PLL) for the emerging applications such 5G and IoT are continuously growing. Compared with the conventional single-path loop based PLL, including the charge pump based PLL, sub-sampling PLL and all-digital PLL, the hybrid dual-path loop based PLL architecture (HDL-PLL) can combine the advantages of all these three kinds of single-path loop based PLL to achieve better performances. This paper first gives an overview of the basics, advantages, and the recent research progress of HDL-PLL. Then, two design examples based on our recent research with their measurement results are introduced to show that the HDL-PLL architecture can effectively improve the PLL performances.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"19 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75492408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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