用于钙钛矿直接x射线探测器的低检测限高线性CMOS读出电路

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI:10.1109/ICSICT49897.2020.9278370

Hao Li, Guangda Niu, Zheng Nie, Jiang Tang, Dongsheng Liu

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引用次数: 0

摘要

本文提出了一种低检出限、高线性度的钙钛矿型直接x射线探测器CMOS读出电路。我们将钙钛矿的输入信号建模为电流源，读出电路包括一个64 ×64四晶体管有源像素传感器(4T APS)像素阵列和一个1.2倍电压放大的放大电路。像素尺寸为20µm×20µm，采用15.5fF MIM电容在集成期间将输入电流转换为电压。设计了相关双样本(CDS)结构来降低随机噪声。该电路采用中芯国际180nm混合信号工艺设计。在10ms典型集成时间内，钙钛矿电流范围为0-2.25pA，对应的输出电压为-442.5mV-864.7mV。信号线性度超过99%。

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A CMOS Readout Circuit with Low Detection Limit and High Linearity for Perovskite-based Direct X-ray Detector

A CMOS readout circuit with low detection limit and high linearity for perovskite-based direct X-ray detector is proposed in this paper. We model the input signal of perovskite as a current source and the readout circuit includes a 64 ×64 four-transistor active pixel sensor (4T APS) pixel array and an amplification circuit with 1.2× voltage magnification. The pixel size is 20µm×20µm and a 15.5fF MIM capacitor is employed to convert the input current into voltage during the integration time. Correlated double sample (CDS) structure is designed to decrease the random noise. The circuit is designed with SMIC 180nm Mixed Signal process. The current range of perovskite is 0-2.25pA and the corresponding output voltage is -442.5mV-864.7mV within 10ms typical integration time. The linearity of signal exceeds 99%.

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来源期刊

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)

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