2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)最新文献

RF GaN Device Model Survey and Model Parameter Extraction Flows 射频GaN器件模型综述及模型参数提取流程

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278132

Raj Sodhi, R. Tinti, M. Dunn, Ma Long

引用次数: 2

A Low-Pass Sense and Control Circuit for Switching Amplifier in Wideband Hybrid Envelope Tracking Supply Modulator 宽带混合包络跟踪电源调制器中开关放大器的低通检测与控制电路

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278281

Xueli Zhang, Peng Xu, Zhiliang Hong

引用次数: 0

A 681 GOPS/W~3.59 TOPS/W CNN Accelerator Based on Novel Data Flow Scheduling Scheme 基于新数据流调度方案的681 GOPS/W~3.59 TOPS/W CNN加速器

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278238

Yan Li, Xiaoling Ding, Haichuan Yang, Xuan Zhang, Yu Gong, Bo Liu

引用次数: 2

Design and Implementation of NFC Smart Card SoC with eSTT-MRAM IP 基于eSTT-MRAM IP的NFC智能卡SoC设计与实现

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278138

Kaiwen Lu, Xingjie Liu, Yong Chen, Dongsheng Liu, Bo Liu, Liang Wu

引用次数: 1

Small-world-based Structural Pruning for Efficient FPGA Inference of Deep Neural Networks 基于小世界结构剪枝的高效FPGA深度神经网络推理

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278024

Gokul Krishnan, Yufei Ma, Yu Cao

{"title":"Small-world-based Structural Pruning for Efficient FPGA Inference of Deep Neural Networks","authors":"Gokul Krishnan, Yufei Ma, Yu Cao","doi":"10.1109/ICSICT49897.2020.9278024","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278024","url":null,"abstract":"DNN pruning approaches usually trim model parameters without exploiting the intrinsic graph properties and hardware preferences. As a result, an FPGA accelerator may not directly benefit from such random pruning, with additional cost on indexing and control modules. Inspired by the observation that the brain and real-world networks follow a Small-World model, we propose a graph-based progressive structural pruning technique that integrates local clusters and global sparsity in the Small-World graph and the data locality in the FPGA dataflow. The proposed technique hierarchically trims the DNN into a sparse graph before training, which follows both the Small-World property and FPGA dataflow preferences, such as grouped non-zero and zero parameters to skip data load and corresponding computation. The pruned model is then trained for a given dataset and fine-tuned to achieve the best accuracy. We evaluate the proposed technique for multiple DNNs with different datasets. It achieves state-of-the-art sparsity ratio of up to 76% for CIFAR-10, 84% for CIFAR-100, and 76% for the SVHN datasets. Moreover, the generated sparse DNN achieves up to 4× improvement in throughput for an output stationary FPGA architecture across different DNNs with a marginal hardware overhead.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"198 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77485417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Reinforcement Learning Driven Physical Synthesis : (Invited Paper) 强化学习驱动物理合成:(特邀论文)

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278350

Zhuolun He, Lu Zhang, Peiyu Liao, Yuzhe Ma, Bei Yu

引用次数: 0

A Multi-band CMOS VCO Based on Triple-coil Inductors 基于三圈电感的多频带CMOS压控振荡器

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278156

Peng Yu, Zhijian Chen, Bin Li, Xiao-Ling Lin, Changhua Zhou

引用次数: 0

Non-volatile In Memory Dual-Row X(N)OR Operation with Write Back Circuit Based on 1T1C FeRAM 基于1T1C FeRAM的非易失性内存双行X(N)OR写回电路

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278353

Wang Qiao, Yuling Zhao, Jianguo Yang, Chao Liu, Pengfei Jiang, Qingting Ding, Tiancheng Gong, Q. Luo, H. Lv, Ming Liu

{"title":"Non-volatile In Memory Dual-Row X(N)OR Operation with Write Back Circuit Based on 1T1C FeRAM","authors":"Wang Qiao, Yuling Zhao, Jianguo Yang, Chao Liu, Pengfei Jiang, Qingting Ding, Tiancheng Gong, Q. Luo, H. Lv, Ming Liu","doi":"10.1109/ICSICT49897.2020.9278353","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278353","url":null,"abstract":"Von Neumann computing architecture system has the characteristic of high energy consumption and slow speed due to the memory bottlenecks of hardware platforms when it processes computing tasks that rely on big data. The drawbacks of memory bottlenecks in traditional structures can be improved significantly using PIM (processing-in-memory) architectures. FeRAM (ferroelectric memory) is a novel memory with the advantages of simple structure, high integration and low power consumption. Thus, it has always been considered as one of the most proper memories for PIM. In this paper, FeRAM was designed as memory and converted to basic computing cells, based on its charge sharing function. A mechanism of two-line activation was adopted during the process of X(N)OR. Then, peripheral circuits were moderately modified to implement bit-by-bit X(N)OR operations between operands stored in the same bit line. Besides, the simulation of X(N)OR logic was carried out. The final simulation results show that the speed, area and power consumption of current FeRAM-based logic operations are improved. The research can be used to enhance the performance of arithmetic logic units for future PIM.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"9 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85240126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Design of A Wide-Range PLL Based on Dual VCO Technique for Sub-1G IoT Application 基于双VCO技术的亚1g物联网宽量程锁相环设计

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278135

Ming Wang, Miao-Xing Xie, Xianglong Li, Yabin Sun, Xiaojin Li, Yanfang Ding, Yanling Shi

引用次数: 1

Study of Silicon Controlled Rectifier Devices with Different Dimensions for ESD Protection 不同尺寸可控硅整流器ESD防护研究

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278319

Yize Wang, Junmin He, Y. Hu, Yubo Wang, Yuan Wang

引用次数: 1