发布求助
文献互助 智能选刊 最新文献

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)最新文献

筛选
英文 中文
Detailed Routing Short Violations Prediction Method Using Graph Convolutional Network 基于图卷积网络的详细路由短违规预测方法
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278302
Xuan Chen, Zhixiong Di, Wei Wu, Quanyuan Feng, Jiang-Yi Shi
{"title":"Detailed Routing Short Violations Prediction Method Using Graph Convolutional Network","authors":"Xuan Chen, Zhixiong Di, Wei Wu, Quanyuan Feng, Jiang-Yi Shi","doi":"10.1109/ICSICT49897.2020.9278302","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278302","url":null,"abstract":"With the continuous shrink of IC manufacturing process, how to accurately predict the routing violations before detailed routing is becoming more and more important to improve the placement quality. In this paper, we propose a detailed routing short violations prediction model based on the Graph Convolutional Network (GCN). Based on the key features extracted from the placement and detailed routing stage separately, we train a GCN model to build a map relationship between these two stages. Through this model, we can predict the detailed routing short violations at placement stage successfully. Experiments show that the average prediction accuracy of our model is 94% which is higher than existing method based on machine learning.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"49 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74664167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Research and Development of QR Code Steganography Based on JSteg Algorithm in DCT Domain DCT领域基于JSteg算法的二维码隐写技术研究与开发
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278285
Yanfei Sun, Mengyuan Yu, Junyu Wang
{"title":"Research and Development of QR Code Steganography Based on JSteg Algorithm in DCT Domain","authors":"Yanfei Sun, Mengyuan Yu, Junyu Wang","doi":"10.1109/ICSICT49897.2020.9278285","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278285","url":null,"abstract":"Using steganography for data hiding is becoming a main subject to ensure both information security and picture quality. Traditional steganography algorithms usually convert secret information into a binary string and embed it in the pixel data of the cover image. In order to ensure the information security as well as convenient transmission, this work studies the steganography algorithm of embedding the QR code containing secret information into the cover image, based on the JSteg algorithm. Secret messages with different sizes have been tested by many cover images and standard parameters have adopted to verify the efficiency. According to the experimental results, all the PSNR in a value that is greater than 47.6 dB. The proposed method has high security and more imperceptibility.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"118 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75829247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Progress of Lead-Free Halide Perovskite X-ray Detectors 无铅卤化物钙钛矿x射线探测器的研究进展
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278179
Hainan Zhang, Guanhua Dun, Y. Qiao, D. Xie, T. Ren
{"title":"Progress of Lead-Free Halide Perovskite X-ray Detectors","authors":"Hainan Zhang, Guanhua Dun, Y. Qiao, D. Xie, T. Ren","doi":"10.1109/ICSICT49897.2020.9278179","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278179","url":null,"abstract":"Lead halide perovskite for radiation detection still faces significant challenges despite its exciting progress. The main issues which hinder further development are the toxicity problem of lead and the intrinsic instability for volatile organic parts in lead-based perovskites. Therefore, searching for low-toxic and intrinsically stable perovskite materials have drawn a great attention from the public. In this review, lead-free perovskites are divided into two types: double perovskites type as A2MIMIIX6 and low-dimensional perovskites type as A3W2X9. The synthesis methods of these lead-free perovskites are discussed and the performance on X-ray detection are accordingly summarized. Moreover, a brief outlook on the future development of lead-free perovskites in radiation detection is proposed.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"22 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73785329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Page-Forming Scheme with Ultra-Low Bit-Error-Rate and High Reliability on a 1Mb RRAM Chip 一种基于1Mb RRAM芯片的超低误码率和高可靠性的页面形成方案
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278288
Junyi Wang, L. Pan, B. Gao, Dabin Wu, Jianshi Tang, Huaqiang Wu, H. Qian
{"title":"A Novel Page-Forming Scheme with Ultra-Low Bit-Error-Rate and High Reliability on a 1Mb RRAM Chip","authors":"Junyi Wang, L. Pan, B. Gao, Dabin Wu, Jianshi Tang, Huaqiang Wu, H. Qian","doi":"10.1109/ICSICT49897.2020.9278288","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278288","url":null,"abstract":"RRAM is regarded as one of the emerging storage class memory, but the reliability and variability issues still need to be improved. In this work, two-transistors-tow-resistors (2T2R) cell structure and several peripheral circuits are developed, improving the bit-error-rate (BER) significantly. Conventional forming process of RRAM is time consuming, it is another critical issue that should be overcome before mass production. This work proposes a novel flash forming scheme on a specific designed RRAM array. With this verification-free scheme, a page of RRAM cells can be formed simultaneously, reducing the time of forming by orders of magnitude. A 1Mb full chip is designed and fabricated based on the proposed scheme, an ultra-low BER of ~ 10−5 without any error-correction is achieved. Fast speed (<10ns), excellent chip-to-chip uniformity and reliability (>106 cycles, > 10 years@25°C) are also demonstrated on the chip level.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"6 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74577825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Variation Investigation of Junction-less Transistor with Side-wall Charge-plasma Structure Induced by Line Edge Roughness 线边缘粗糙度诱导无结边壁电荷等离子体结构晶体管的变化研究
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278349
Kai Liu, Hung-Chih Chin, H. Lou, Kuan‐Chang Chang, Xinnan Lin
{"title":"Variation Investigation of Junction-less Transistor with Side-wall Charge-plasma Structure Induced by Line Edge Roughness","authors":"Kai Liu, Hung-Chih Chin, H. Lou, Kuan‐Chang Chang, Xinnan Lin","doi":"10.1109/ICSICT49897.2020.9278349","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278349","url":null,"abstract":"In this work, the fluctuations of the electrical characteristics including ON -current, OFF -current, subthreshold swing and threshold voltage, due to line edge roughness (LER) for double-gate charge-plasma junctionless transistor (CPJLT) and side-wall charge-plasma junctionless transistor (S-CPJLT) are explored. Results shows that S-CPJLT has less fluctuations in ON -current while maintaining similar performance of other electrical characteristics. Besides, S-CPJLT has larger ON-current, smaller OFF-current on average. This work indicates that S-CPJLT has greater potential in electronic device development.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"38 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76463279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Photovoltaic and Thermal Energy Combining Harvesting Interface Circuit with MPPT and Single Inductor 一种基于MPPT和单电感的光电与热能结合采集接口电路
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278256
Peichao Zhang, Lianxi Liu
{"title":"A Photovoltaic and Thermal Energy Combining Harvesting Interface Circuit with MPPT and Single Inductor","authors":"Peichao Zhang, Lianxi Liu","doi":"10.1109/ICSICT49897.2020.9278256","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278256","url":null,"abstract":"This paper proposed a photovoltaic and thermal energy combining harvesting interface circuit. The time-multiplexed operating of the power stage circuit can harvest thermal energy and photovoltaic energy simultaneously in a cycle, obtaining high efficiency and a smaller volume of the system. Combined with the open-circuit voltage algorithm, the interface circuit outputs energy at the maximum power point. The proposed interface circuit is implemented in a 0.18 µm standard CMOS process. The simulation results show that the conduction time of the thermal energy path occupies about 50% of the cycle and the conduction time of the photovoltaic energy path occupies about 5% of the cycle. The peak tracking efficiency of photovoltaic energy is 99.1 % and the peak tracking efficiency of thermal energy is 99%. The peak power conversion efficiency of the overall circuit is 89%.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"5 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80070142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Copyright notice 2020 IEEE第15届固态和集成电路技术国际会议(ICSICT) -版权声明
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/icsict49897.2020.9278335
{"title":"2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Copyright notice","authors":"","doi":"10.1109/icsict49897.2020.9278335","DOIUrl":"https://doi.org/10.1109/icsict49897.2020.9278335","url":null,"abstract":"","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"4 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80188536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impacts of Lateral Charge Migration on Data Retention and Read Disturb in 3D Charge-trap NAND Flash Memory 三维电荷阱NAND闪存中横向电荷迁移对数据保留和读取干扰的影响
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278015
Xueyang Peng, Fei Wang, Yachen Kong, Menghua Jia, Xuepeng Zhan, Yuan Li, Jiezhi Chen
{"title":"Impacts of Lateral Charge Migration on Data Retention and Read Disturb in 3D Charge-trap NAND Flash Memory","authors":"Xueyang Peng, Fei Wang, Yachen Kong, Menghua Jia, Xuepeng Zhan, Yuan Li, Jiezhi Chen","doi":"10.1109/ICSICT49897.2020.9278015","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278015","url":null,"abstract":"For deeper insights into the reliabilities of 3D charge-trap (CT) flash memory, we investigated the impacts of lateral charge migration (LCM) on data retention (DR) and read disturb (RD) by TCAD simulations. With discussions on the influence of neighbor cells' states and defect levels, it is found that LCM caused charge accumulation under the external electric fields could be the dominant reason to explain experimentally observed abnormal RD. Our results strongly suggest that appropriate read cycling could be an effective way to retrieve threshold voltage (Vth) down-shifts during data retention.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"24 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83269604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
An IOSGO-CFARAlgorithm based on Clutter Classification and Recognition 基于杂波分类识别的iosgo - cfar算法
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278327
Lintao Li, Jiangyi Shi, Yuanyuan Li, Zhaowei Su, Xuan Liu
{"title":"An IOSGO-CFARAlgorithm based on Clutter Classification and Recognition","authors":"Lintao Li, Jiangyi Shi, Yuanyuan Li, Zhaowei Su, Xuan Liu","doi":"10.1109/ICSICT49897.2020.9278327","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278327","url":null,"abstract":"Constant False Alarm Rate(CFAR)processing is one of the most critical technologies in radar signal processing, and its purpose is to guarantee a constant false alarm rate during the detection for targets. However, the general CFAR processing is predicated on the clutter distribution characteristics, and different clutter distributions correspond to different CFAR processing algorithms. In order to improve detection performance in different clutter distributions, in this paper we proposes an IOSGO-CFAR algorithm, This method uses the number of interference targets that S-CFAR can tolerate to determine whether it is a homogeneous environment or a non-homogeneous environment. When the number of tolerable interference targets is set to zero, this is a homogeneous enviroment and the CA-CFAR algorithm is selected. Once the interference target is detected, this is a nonhomogeneous environment and the OSGO-CFAR algorithm is selected. When CFAR is 10−4, the algorithm simulation of IOSGO-CFAR shows that IOSGO-CFAR has better detection performance. Finally, the verification of FPGA is carried out and the clock frequency can reach 154.967 MHz.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"83 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72866029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SPICE Modeling and Verification of Wafer-Scale MoS2Transistors 晶圆级mos2晶体管的SPICE建模与验证
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278321
Xi Wang, Shunli Ma, Baowen Zhong, Junyan Ren
{"title":"SPICE Modeling and Verification of Wafer-Scale MoS2Transistors","authors":"Xi Wang, Shunli Ma, Baowen Zhong, Junyan Ren","doi":"10.1109/ICSICT49897.2020.9278321","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278321","url":null,"abstract":"This paper presents a SPICE model for the current-voltage (I-V) characteristics of Mos2 field-effect transistors based on the level-62 MOSFET SPICE model template. We simulated both the output characteristics and transfer characteristics of single-layer Mos2 FETs based on the model we built. Model parameters are extracted according to different working region. The root-mean-square error of the I-V characteristics of Mos2 FETs in this paper is extremely small and the simulation speed is fast. In addition, we built an inverter circuit to verify the accuracy of our model, and the simulation results of its voltage transfer characteristics(VTC) match well with the experimental results.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88620540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信