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2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)最新文献

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Impacts of Lateral Charge Migration on Data Retention and Read Disturb in 3D Charge-trap NAND Flash Memory 三维电荷阱NAND闪存中横向电荷迁移对数据保留和读取干扰的影响
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278015
Xueyang Peng, Fei Wang, Yachen Kong, Menghua Jia, Xuepeng Zhan, Yuan Li, Jiezhi Chen
{"title":"Impacts of Lateral Charge Migration on Data Retention and Read Disturb in 3D Charge-trap NAND Flash Memory","authors":"Xueyang Peng, Fei Wang, Yachen Kong, Menghua Jia, Xuepeng Zhan, Yuan Li, Jiezhi Chen","doi":"10.1109/ICSICT49897.2020.9278015","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278015","url":null,"abstract":"For deeper insights into the reliabilities of 3D charge-trap (CT) flash memory, we investigated the impacts of lateral charge migration (LCM) on data retention (DR) and read disturb (RD) by TCAD simulations. With discussions on the influence of neighbor cells' states and defect levels, it is found that LCM caused charge accumulation under the external electric fields could be the dominant reason to explain experimentally observed abnormal RD. Our results strongly suggest that appropriate read cycling could be an effective way to retrieve threshold voltage (Vth) down-shifts during data retention.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"24 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83269604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fully Self-Aligned Homojunction Bottom-Gate Amorphous InGaZnO TFTs with Al Reacted Source/Drain Regions 具有Al反应源/漏区的全自对准同结底栅非晶InGaZnO tft
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278365
Xiaoliang Zhou, Yang Shao, Huan Yang, Q.P. Lin, Lei Lu, Yi Wang, Shengdong Zhang
{"title":"Fully Self-Aligned Homojunction Bottom-Gate Amorphous InGaZnO TFTs with Al Reacted Source/Drain Regions","authors":"Xiaoliang Zhou, Yang Shao, Huan Yang, Q.P. Lin, Lei Lu, Yi Wang, Shengdong Zhang","doi":"10.1109/ICSICT49897.2020.9278365","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278365","url":null,"abstract":"Fully self-aligned homojunction bottom-gate (HJBG) amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) are realized in this work. A backside-exposure process is employed to fulfill the self-alignment of the gate and SiO2 channel protection layer (PL) using the metal gate as a mask, and the conductive source/drain regions self-aligned with the PL are formed by metal Al reaction treatment. The fabricated TFTs exhibit good device performance. The influence of backside exposure time is studied, and an increase in parasitic resistance is observed when the exposure time is shorter than 16 s which is inferred to be caused by the increased spreading resistance at the edge of the source/drain regions.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"2 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87412338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A DTCO approach on DRAM bit line capacitance and sensing margin improvement 一种改进DRAM位线电容和感知余量的DTCO方法
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278287
Qinghua Han, M. Cai, Blacksmith Wu, Kanyu Cao
{"title":"A DTCO approach on DRAM bit line capacitance and sensing margin improvement","authors":"Qinghua Han, M. Cai, Blacksmith Wu, Kanyu Cao","doi":"10.1109/ICSICT49897.2020.9278287","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278287","url":null,"abstract":"A Design Technology Co-Optimization (DTCO) study was performed on DRAM array bit line capacitance (C_BL) for optimum array sensing margin. C_BL related structural parameters involving bit line width, bit line spacer width, spacer film stacks, and cell contact width were explored. C_BL, bit line resistance (R_BL) and cell contact resistance (R_CC) were calculated correspondingly, and reflects onto the relative changes of sensing margin (Δ Vsm) and writing recovery time (Δ tWR). The tradeoff between Δ Vsm and Δ tWR were revealed. Considering the process feasibility, optimum C_BL are proposed, sensing margin gain and tWR loss are evaluated.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"5 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88530157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and Comparison of FIR Filter Based on DSP Builder and HDL Coder 基于DSP Builder和HDL编码器的FIR滤波器设计与比较
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278259
Qin Huang, Zilin Wang
{"title":"Design and Comparison of FIR Filter Based on DSP Builder and HDL Coder","authors":"Qin Huang, Zilin Wang","doi":"10.1109/ICSICT49897.2020.9278259","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278259","url":null,"abstract":"DSP Builder and HDL Coder are common VHDL /Verilog code generation tools, but the comparison of the two tools has not been fully explored. In this paper, an FIR filter with the same structure, word length and filter coefficients is built, and Verilog code is generated by using the above two tools respectively. Then, we compare the resource consumption in Quartus II. The results show that DSP Builder has advantages in the consumption of pins, and HDL Coder has advantages in the consumption of logic elements. This guides us to select specific code generation tools according to the actual needs.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"112 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88804667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Research and Development of QR Code Steganography Based on JSteg Algorithm in DCT Domain DCT领域基于JSteg算法的二维码隐写技术研究与开发
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278285
Yanfei Sun, Mengyuan Yu, Junyu Wang
{"title":"Research and Development of QR Code Steganography Based on JSteg Algorithm in DCT Domain","authors":"Yanfei Sun, Mengyuan Yu, Junyu Wang","doi":"10.1109/ICSICT49897.2020.9278285","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278285","url":null,"abstract":"Using steganography for data hiding is becoming a main subject to ensure both information security and picture quality. Traditional steganography algorithms usually convert secret information into a binary string and embed it in the pixel data of the cover image. In order to ensure the information security as well as convenient transmission, this work studies the steganography algorithm of embedding the QR code containing secret information into the cover image, based on the JSteg algorithm. Secret messages with different sizes have been tested by many cover images and standard parameters have adopted to verify the efficiency. According to the experimental results, all the PSNR in a value that is greater than 47.6 dB. The proposed method has high security and more imperceptibility.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"118 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75829247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Fast Settling Low Noise Ring Amplifier for High Speed Pipelined SAR ADCs 一种用于高速流水线SAR adc的快速沉降低噪声环形放大器
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278374
Longbo Fan, Bingbing Ma, N. Yan, Yun Yin, Hongtao Xu
{"title":"A Fast Settling Low Noise Ring Amplifier for High Speed Pipelined SAR ADCs","authors":"Longbo Fan, Bingbing Ma, N. Yan, Yun Yin, Hongtao Xu","doi":"10.1109/ICSICT49897.2020.9278374","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278374","url":null,"abstract":"In this paper, a fast-settling ring amplifier (ringamp) with high linearity and low noise is presented. Implemented in 40 nm CMOS technology, the ringamp is shown to meet the requirements of residue amplifiers used in pipelined successive-approximation-register (SAR) analog-to-digital converters (ADCs). A modified common mode feedback (CMFB) loop makes the amplifier robust enough to work well over all process corners, which solves the long-existing problem in traditional ringamps. Simulation results show that signal to distortion ratio (SDR) is above 50 dB in various temperature/corner conditions.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"21 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75457747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Ultra-thin-barrier AlGaN/GaN MIS-gated Hybrid Anode Diode Featuring Improved High-temperature Reverse Blocking Characteristic 一种新型超薄势垒AlGaN/GaN错门控杂化阳极二极管，具有改进的高温反向阻滞特性
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278128
Liyang Zhu, Qi Zhou, Kuangli Chen, Xiu Yang, Jiacheng Lei, Zhihua Luo, Chunhua Zhou, K. J. Chen, Bo Zhang
{"title":"A Novel Ultra-thin-barrier AlGaN/GaN MIS-gated Hybrid Anode Diode Featuring Improved High-temperature Reverse Blocking Characteristic","authors":"Liyang Zhu, Qi Zhou, Kuangli Chen, Xiu Yang, Jiacheng Lei, Zhihua Luo, Chunhua Zhou, K. J. Chen, Bo Zhang","doi":"10.1109/ICSICT49897.2020.9278128","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278128","url":null,"abstract":"In this work, a novel MIS-gated hybrid anode diode (MG-HAD) based on ultra-thin-barrier (UTB) AlGaN/GaN heterostructure is demonstrated to exhibit a superior reverse blocking characteristic. An ultra-low reverse leakage of ~1.1 × 10−7 A/mm observed in room-temperature (RT) and the breakdown voltage (BV) dominated by buffer breakdown, verify the excellent reverse blocking characteristic originated from the ALD-Ah03 insulator in MIS-gate structure. More importantly, the reverse leakage current maintains respectably low at high temperature (HT) up to 200 °C, which is as low as ~5.1 × 10−7 A/mm at 200 °C and is among the best reported results at the comparable reverse bias voltage and temperature.. Such a great superiority in HT reverse blocking capability indicates that the UTB MG-HAD is a promising device structure and technology for high performance GaN power diodes.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"26 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72707893","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Digital Synthesizable Full Common-mode Input Range Dynamic Voltage Comparator 一种数字合成全共模输入范围动态电压比较器
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278145
Min Li, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
{"title":"A Digital Synthesizable Full Common-mode Input Range Dynamic Voltage Comparator","authors":"Min Li, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng","doi":"10.1109/ICSICT49897.2020.9278145","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278145","url":null,"abstract":"This paper presents a digital synthesizable full common-mode input range dynamic voltage comparator (FCMRDVC). It is a modified version of the rail-to-rail dynamic voltage comparator (RRDVC), with a view to a real rail-to-rail common-mode input range (CMR). The proposed FCMRDVC is designed and synthesized in 28-nm CMOS technology with the active area of 43.2µm2, and the simulation results show the maximum power consumption of 7.5nW under 0.3V power supply voltage (VDD) and CMR of 0-VDD.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"32 11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88384711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An IOSGO-CFARAlgorithm based on Clutter Classification and Recognition 基于杂波分类识别的iosgo - cfar算法
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278327
Lintao Li, Jiangyi Shi, Yuanyuan Li, Zhaowei Su, Xuan Liu
{"title":"An IOSGO-CFARAlgorithm based on Clutter Classification and Recognition","authors":"Lintao Li, Jiangyi Shi, Yuanyuan Li, Zhaowei Su, Xuan Liu","doi":"10.1109/ICSICT49897.2020.9278327","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278327","url":null,"abstract":"Constant False Alarm Rate(CFAR)processing is one of the most critical technologies in radar signal processing, and its purpose is to guarantee a constant false alarm rate during the detection for targets. However, the general CFAR processing is predicated on the clutter distribution characteristics, and different clutter distributions correspond to different CFAR processing algorithms. In order to improve detection performance in different clutter distributions, in this paper we proposes an IOSGO-CFAR algorithm, This method uses the number of interference targets that S-CFAR can tolerate to determine whether it is a homogeneous environment or a non-homogeneous environment. When the number of tolerable interference targets is set to zero, this is a homogeneous enviroment and the CA-CFAR algorithm is selected. Once the interference target is detected, this is a nonhomogeneous environment and the OSGO-CFAR algorithm is selected. When CFAR is 10−4, the algorithm simulation of IOSGO-CFAR shows that IOSGO-CFAR has better detection performance. Finally, the verification of FPGA is carried out and the clock frequency can reach 154.967 MHz.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"83 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72866029","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
SPICE Modeling and Verification of Wafer-Scale MoS2Transistors 晶圆级mos2晶体管的SPICE建模与验证
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278321
Xi Wang, Shunli Ma, Baowen Zhong, Junyan Ren
{"title":"SPICE Modeling and Verification of Wafer-Scale MoS2Transistors","authors":"Xi Wang, Shunli Ma, Baowen Zhong, Junyan Ren","doi":"10.1109/ICSICT49897.2020.9278321","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278321","url":null,"abstract":"This paper presents a SPICE model for the current-voltage (I-V) characteristics of Mos2 field-effect transistors based on the level-62 MOSFET SPICE model template. We simulated both the output characteristics and transfer characteristics of single-layer Mos2 FETs based on the model we built. Model parameters are extracted according to different working region. The root-mean-square error of the I-V characteristics of Mos2 FETs in this paper is extremely small and the simulation speed is fast. In addition, we built an inverter circuit to verify the accuracy of our model, and the simulation results of its voltage transfer characteristics(VTC) match well with the experimental results.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88620540","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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