Design and Comparison of FIR Filter Based on DSP Builder and HDL Coder

Abstract

DSP Builder and HDL Coder are common VHDL /Verilog code generation tools, but the comparison of the two tools has not been fully explored. In this paper, an FIR filter with the same structure, word length and filter coefficients is built, and Verilog code is generated by using the above two tools respectively. Then, we compare the resource consumption in Quartus II. The results show that DSP Builder has advantages in the consumption of pins, and HDL Coder has advantages in the consumption of logic elements. This guides us to select specific code generation tools according to the actual needs.