A DTCO approach on DRAM bit line capacitance and sensing margin improvement

Abstract

A Design Technology Co-Optimization (DTCO) study was performed on DRAM array bit line capacitance (C_BL) for optimum array sensing margin. C_BL related structural parameters involving bit line width, bit line spacer width, spacer film stacks, and cell contact width were explored. C_BL, bit line resistance (R_BL) and cell contact resistance (R_CC) were calculated correspondingly, and reflects onto the relative changes of sensing margin (Δ Vsm) and writing recovery time (Δ tWR). The tradeoff between Δ Vsm and Δ tWR were revealed. Considering the process feasibility, optimum C_BL are proposed, sensing margin gain and tWR loss are evaluated.