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2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)最新文献

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Implementation of Convolutional Neural Network with Co-design of High-Level Synthesis and Verilog HDL 高阶合成与Verilog HDL协同设计卷积神经网络的实现
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278149
Hejie Yu, Jun Cheng, X. Zhang, Yuzhe Gao, K. Mei
{"title":"Implementation of Convolutional Neural Network with Co-design of High-Level Synthesis and Verilog HDL","authors":"Hejie Yu, Jun Cheng, X. Zhang, Yuzhe Gao, K. Mei","doi":"10.1109/ICSICT49897.2020.9278149","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278149","url":null,"abstract":"In recent years, Convolutional Neural Networks(CNNs) have been widely adopted for image classification and target recognition. As one of CNN's main hardware implementation platforms, FPGA has its advantages of high flexibility, excellent trade-off between performance and power, but still has the problems of complex developing processes and poor adaptability for various algorithm models. Therefore, a high-performance and fast hardware implementation architecture adaptation to the CNNs is presented in the paper. The hardware architecture is designed with co-design of High-Level Synthesis(HLS) and Verilog HDL, which simplifies the design process and ensures performance. And it adopts the variables parameterization to deal with the problem of pool model adaptability. With row-by-row calculation, the circuits adopt the layered parallelism to ensure the flexibility of convolution and the pipeline parallel calculation to improve the speed. The paper achieves an overall average 359.7GOP/s for the AlexNet on Xilinx ZCU104 platform.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"10 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87309421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Complex Placement Region Handling Based on Electrostatic System Modeling 基于静电系统建模的复杂放置区域处理
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278229
Yongyi Guo, Yingjie Wu, Zhipeng Huang, Jianli Chen
{"title":"Complex Placement Region Handling Based on Electrostatic System Modeling","authors":"Yongyi Guo, Yingjie Wu, Zhipeng Huang, Jianli Chen","doi":"10.1109/ICSICT49897.2020.9278229","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278229","url":null,"abstract":"With the additional fence region constraints in modern circuit designs, the VLSI placement problem has become more complex and challenging. A placement solution without considering fence region constraints may cause many problems in the legalization stage and result in an inferior placement. In this paper, we present an effective placement region handling method based on the two-dimensional electrostatic system modeling. Under the fence region constrains, we first generate multiple density maps for assigning cells to their respective fence regions. Then, we further add proper fence filler nodes to each density map, which is able to squeeze fence cells to be placed closer. The placement performance is validated through experiments on ISPD 2015 benchmarks. Experimental results show that, compared with the state-of-the-art placer NTUplace4dr, our proposed method not only reduces the wirelength by 9.9% but also achieves 5x faster runtime.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"90 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89959767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A novel SOI-based ridge waveguide SiGe Heterojunction Phototransistor 一种新型soi基脊波导SiGe异质结光电晶体管
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278192
Ce Bian, Hongyun Xie, M. Guo, Yin Sha, Yang Xiang, X. Liu, Wanrong Zhang
{"title":"A novel SOI-based ridge waveguide SiGe Heterojunction Phototransistor","authors":"Ce Bian, Hongyun Xie, M. Guo, Yin Sha, Yang Xiang, X. Liu, Wanrong Zhang","doi":"10.1109/ICSICT49897.2020.9278192","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278192","url":null,"abstract":"A kind of SiGe heterojunction phototransistor with gradual coupled ridge waveguide based on silicon-on-insulator (SOI SiGe GRC HPT) is designed and optimized to improve its optical responsivity and working speed. When the width and length of the ridge waveguide are optimized as 3um and 20um separately, the ridge waveguide based on SOI provide the same limitation for TE mode and TM mode and the suitable propagation path for incident light. The maximum characteristic frequency of SOI SiGe GRC HPT is 102GHz, its saturation current is 20mA and its optical responsivity is 0.5 A/W.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"38 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84042912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28GHz 6-bit Two-stage Vector-sum Phase Shifter with Low RMS Error for 5G Mobile Communication 5G移动通信用低有效值误差的28GHz 6位两级矢量和移相器
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278260
Xingyu Qi, Shuyu Liu, Zongyuan Zheng, Bo Wang, Xing Zhang
{"title":"A 28GHz 6-bit Two-stage Vector-sum Phase Shifter with Low RMS Error for 5G Mobile Communication","authors":"Xingyu Qi, Shuyu Liu, Zongyuan Zheng, Bo Wang, Xing Zhang","doi":"10.1109/ICSICT49897.2020.9278260","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278260","url":null,"abstract":"This paper presents a 28GHz 6-bit active phase shifter in 65nm CMOS for 5G mobile communication. To lower the RMS error, a novel two-stage vector-sum architecture is proposed, which divides the 6-bit phase shifter into four 4-bit sub phase shifters and one active vector combiner. The 4-bit sub phase shifters are implemented just by switches and differential gain units which can also lower the RMS error apparently. Through the optimization of circuit topologies, the RMS error of the phase shifter is significantly lowered. The 6-bit phase shifter results in a simulated RMS gain error of 0.21dB and RMS phase error of 1.2° between 27.5-28.35GHz. The total current consumption is 11.8mA from a 1.2V supply voltage and the core size is 0.86×0.85mm2.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"14 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84428816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Novel Radiation Hardened Memory Cell Design for Nanometer Technology 纳米技术新型辐射硬化存储单元设计
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278182
Liyi Xiao, Hongchen Li, Jie Li, He Liu
{"title":"Novel Radiation Hardened Memory Cell Design for Nanometer Technology","authors":"Liyi Xiao, Hongchen Li, Jie Li, He Liu","doi":"10.1109/ICSICT49897.2020.9278182","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278182","url":null,"abstract":"In this paper, a novel radiation hardened memory cell (RH-10T) using 10 transistors is proposed to tolerate single event upset for nanometer technology. Simulation results have indicated that the proposed RH-10T cell has high reliability, small read and write access time and acceptable power consumption.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"30 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86184940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A VCO-Based Continuous Time Delta-sigma ADC with An Alternative Feedforward Scheme VCO 基于VCO的可选前馈方案的连续时间Delta-sigma ADC
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278289
Mengying Hu, Yuekang Guo, J. Jin
{"title":"A VCO-Based Continuous Time Delta-sigma ADC with An Alternative Feedforward Scheme VCO","authors":"Mengying Hu, Yuekang Guo, J. Jin","doi":"10.1109/ICSICT49897.2020.9278289","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278289","url":null,"abstract":"A Voltage Controlled Oscillator (VCO) based continuous-time Delta-Sigma analog-to-digital converter (ADC) with an alternative new feedforward VCO scheme contributing to higher oscillation frequency within VCO-Based quantizer is explored in this paper. Fourth-Order noise shaping is achieved using three operational transconductance amplifiers (OTAs) and VCO acting as integrator and quantizer. Meanwhile, the excess loop delay (ELD) introduced by the finite gain-bandwidth product of OTAs is compensated by zero-order path in the loop filter to reduce the power consumption further. The simulation results indicate that this prototype achieves a SNDR of 72.17 dB over 10MHz bandwidth sampling at 400MHz while consumes 24mW for a 1.8V supply in 180nm CMOS technology.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"13 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82890712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Proceedings 2020 IEEE第十五届固态与集成电路技术国际会议论文集
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/icsict49897.2020.9278348
Wei Cheng, Guangnan Zhou, Fanming Zeng, Yang Jiang, Lingli Jiang, Qing Wang, Hongyu Yu, Jin Wei, Han Xu, Ruiliang Xie, K. J. Chen, Yize Wang, Yi Hu, Dun-Shan Yu, Xiaojie Xu, Xiaochuan Deng, Yunpeng Xing, Yi Wen, Zhiqiang Li, Xu Li, Bo Zhang, Wei Huang, Xuan Li
{"title":"2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Proceedings","authors":"Wei Cheng, Guangnan Zhou, Fanming Zeng, Yang Jiang, Lingli Jiang, Qing Wang, Hongyu Yu, Jin Wei, Han Xu, Ruiliang Xie, K. J. Chen, Yize Wang, Yi Hu, Dun-Shan Yu, Xiaojie Xu, Xiaochuan Deng, Yunpeng Xing, Yi Wen, Zhiqiang Li, Xu Li, Bo Zhang, Wei Huang, Xuan Li","doi":"10.1109/icsict49897.2020.9278348","DOIUrl":"https://doi.org/10.1109/icsict49897.2020.9278348","url":null,"abstract":"A Novel Shortest-distance Path-based Multicast Routing Algorithm for Network-on-Chips A Low-Power 16-Channel SiPM Readout Front-end with a Shared SAR ADC in 180 nm Studying the Reliability of Ge nFinFETs by the Normalized Input-referred Voltage Noise Interconnect Structures BEOL A Two-ASIC Front-End for MEMS Accelerometers A Photovoltaic and Thermal Energy Combining Harvesting Interface Circuit with MPPT and Single High Dynamic Range Pixel Circuit with High-voltage Protection for 128×128 Linear-mode APD high-efficiency WPT system with dual-output and enhanced coupling Study on Trapping HEMTs The Ultra-Wideband 0.5-15GHz LNA Reconfigurable Receiver System 28 nm A Ka-Band High-Gain and Wideband mmW Down-Conversion Mixer for 5G Communication Applications The Superjunction Device with Optimized Process Window of Breakdown Voltage low power readout circuit for 16-bit Speed DAC R2R An Impedance Calibration Method Based on Temperature and Process Monitor for High-Performance Bipolar GaN Diode Realized Broadened Quantum Well Three-Dimensional Enhancement-Type GaN HEMT High Power Transmission Capability Extended Well A decimation filter Sigma delta modulator FMCW transceiver","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"94 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83885006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Modified Dropout and Maxout based on the MNN for improving accuracy 改进了基于MNN的Dropout和Maxout，提高了精度
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278252
Chao Wang, Xiaojing Zha, Yinshui Xia
{"title":"Modified Dropout and Maxout based on the MNN for improving accuracy","authors":"Chao Wang, Xiaojing Zha, Yinshui Xia","doi":"10.1109/ICSICT49897.2020.9278252","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278252","url":null,"abstract":"Memristor crossbar array is an emerged architecture suitable for matrix computation. Memristor based neural networks (MNN) address the speed and energy efficiency issues in computing hardware. However, there are still a lot of problems with memristor, and the limited size of memristor crossbar resulting in the accuracy of the MNN is lower than conventional neural networks (CNNs). In this paper, a modified Dropout and Maxout based MNN for improving the accuracy of the MNN is proposed. A three-layer memristor based multilayer Perceptron (MLP) in 64*128 crossbar is built to perform MNIST image recognition. The experiment results demonstrate that the in-situ training of the MLP achieves a high accuracy near 96.5% with Dropout and Maxout.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"46 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90544575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Proceedings 2020 IEEE第十五届固态与集成电路技术国际会议论文集
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/icsict49897.2020.9278283
Shao-Wei Yu, Xiaona Zhu, T. Tang
{"title":"2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Proceedings","authors":"Shao-Wei Yu, Xiaona Zhu, T. Tang","doi":"10.1109/icsict49897.2020.9278283","DOIUrl":"https://doi.org/10.1109/icsict49897.2020.9278283","url":null,"abstract":"","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"8 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90644984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Statistical Analysis Method for Reliability Data of Aerospace Components Based on Association Rules 基于关联规则的航天零部件可靠性数据统计分析方法
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278224
Chengzhi Jiang, Xiaoming Fan
{"title":"A Statistical Analysis Method for Reliability Data of Aerospace Components Based on Association Rules","authors":"Chengzhi Jiang, Xiaoming Fan","doi":"10.1109/ICSICT49897.2020.9278224","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278224","url":null,"abstract":"In this paper, as the aerospace components reliability test data resources are rich, randomness, characteristics of discrete, draw lessons from the analysis of large data, in this paper, a method based on association rule mining data statistical analysis is proposed, using this method, easily neglected, useful data model or rules can be excavated, this method provide data support for quality assurance model components.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"27 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80341736","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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