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A DTCO approach on DRAM bit line capacitance and sensing margin improvement 一种改进DRAM位线电容和感知余量的DTCO方法
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278287
Qinghua Han, M. Cai, Blacksmith Wu, Kanyu Cao
{"title":"A DTCO approach on DRAM bit line capacitance and sensing margin improvement","authors":"Qinghua Han, M. Cai, Blacksmith Wu, Kanyu Cao","doi":"10.1109/ICSICT49897.2020.9278287","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278287","url":null,"abstract":"A Design Technology Co-Optimization (DTCO) study was performed on DRAM array bit line capacitance (C_BL) for optimum array sensing margin. C_BL related structural parameters involving bit line width, bit line spacer width, spacer film stacks, and cell contact width were explored. C_BL, bit line resistance (R_BL) and cell contact resistance (R_CC) were calculated correspondingly, and reflects onto the relative changes of sensing margin (Δ Vsm) and writing recovery time (Δ tWR). The tradeoff between Δ Vsm and Δ tWR were revealed. Considering the process feasibility, optimum C_BL are proposed, sensing margin gain and tWR loss are evaluated.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"5 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88530157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Novel Radiation Hardened Memory Cell Design for Nanometer Technology 纳米技术新型辐射硬化存储单元设计
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278182
Liyi Xiao, Hongchen Li, Jie Li, He Liu
{"title":"Novel Radiation Hardened Memory Cell Design for Nanometer Technology","authors":"Liyi Xiao, Hongchen Li, Jie Li, He Liu","doi":"10.1109/ICSICT49897.2020.9278182","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278182","url":null,"abstract":"In this paper, a novel radiation hardened memory cell (RH-10T) using 10 transistors is proposed to tolerate single event upset for nanometer technology. Simulation results have indicated that the proposed RH-10T cell has high reliability, small read and write access time and acceptable power consumption.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"30 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86184940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fully Self-Aligned Homojunction Bottom-Gate Amorphous InGaZnO TFTs with Al Reacted Source/Drain Regions 具有Al反应源/漏区的全自对准同结底栅非晶InGaZnO tft
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278365
Xiaoliang Zhou, Yang Shao, Huan Yang, Q.P. Lin, Lei Lu, Yi Wang, Shengdong Zhang
{"title":"Fully Self-Aligned Homojunction Bottom-Gate Amorphous InGaZnO TFTs with Al Reacted Source/Drain Regions","authors":"Xiaoliang Zhou, Yang Shao, Huan Yang, Q.P. Lin, Lei Lu, Yi Wang, Shengdong Zhang","doi":"10.1109/ICSICT49897.2020.9278365","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278365","url":null,"abstract":"Fully self-aligned homojunction bottom-gate (HJBG) amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) are realized in this work. A backside-exposure process is employed to fulfill the self-alignment of the gate and SiO2 channel protection layer (PL) using the metal gate as a mask, and the conductive source/drain regions self-aligned with the PL are formed by metal Al reaction treatment. The fabricated TFTs exhibit good device performance. The influence of backside exposure time is studied, and an increase in parasitic resistance is observed when the exposure time is shorter than 16 s which is inferred to be caused by the increased spreading resistance at the edge of the source/drain regions.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"2 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87412338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Physical and Electrical Characterization of Doped Amorphous Silicon Resistor 掺杂非晶硅电阻器的物理和电学特性
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278180
Xiaolan Zhong, Xiaoxu Kang, Ruoxi Shen
{"title":"Physical and Electrical Characterization of Doped Amorphous Silicon Resistor","authors":"Xiaolan Zhong, Xiaoxu Kang, Ruoxi Shen","doi":"10.1109/ICSICT49897.2020.9278180","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278180","url":null,"abstract":"Amorphous Silicon (Si) is widely used in CMOS technology, and now applications can be found in MEMs/Sensor products because of its remarkable performance. In this paper, low temperature PECVD amorphous Si process was developed at 200mm CMOS BEOL with low stress at about -30MPa (compressive mode), and there is no peeling or crack problem for the film deposition. Good thickness and sheet resistance uniformity can be achieved of the amorphous Si film. Its thickness uniformity can reach 0.56%, and Rs uniformity can reach 1.22%. Then it was used to fabricate sensing resistor for temperature sensor application, which was defined by thin TiTiN metal layer pattern. To achieve good contact performance, Ar plasma etching process was introduced before metal layer deposition, and its etch rate can be well controlled. From the IV curve, it can be seen that good ohmic contact can be achieved. High selectivity thin metal layer etching process was developed with no process damage to amorphous Si, and 49 point resistance uniformity within wafer can be controlled to less than 2%. Thermal coefficient of resistance (TCR) was measured from 25°C to 40°C, and TCR value can reach at about 1.88%. 1/f Noise performance was evaluated for the resistor, and 1/f noise power at 100Hz can be controlled to -148dB. The measured data of doped amorphous Si resistor can well meet requirements of temperature based sensor.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"94 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73069752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Real-Time 2.4-GHz Doppler Radar System with All Functionalities on Board for Vital Signal Detection 实时2.4 ghz多普勒雷达系统，具有机载生命信号检测的所有功能
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278303
Wei Ma, Zhiming Xiao, Dongyang Tang, Fei Liu, Weibo Hu
{"title":"A Real-Time 2.4-GHz Doppler Radar System with All Functionalities on Board for Vital Signal Detection","authors":"Wei Ma, Zhiming Xiao, Dongyang Tang, Fei Liu, Weibo Hu","doi":"10.1109/ICSICT49897.2020.9278303","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278303","url":null,"abstract":"The protype of a 2.4-GHz zero-IF Doppler radar system with all functionalities on board for real-time vital sign detection is implemented and presented in this paper. The radar system accomplishes RF front end, base-band analog processing, analog-to-digital conversion, digital signal processing for the vital-sign signal extraction and the numeric and graphic result display. In the system, a Sallen-Key filter and a FPGA development board are used to remove interferences, adjust gain, and collect and process raw data. Experiments show that the respiration and heartbeat can be clearly detected when a person sitting at 1 meter away from the proposed radar. Both the realtime waveform and spectrum analysis are displayed on a separate LCD through an VGA interface.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"20 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82409793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Proceedings 2020 IEEE第十五届固态与集成电路技术国际会议论文集
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/icsict49897.2020.9278348
Wei Cheng, Guangnan Zhou, Fanming Zeng, Yang Jiang, Lingli Jiang, Qing Wang, Hongyu Yu, Jin Wei, Han Xu, Ruiliang Xie, K. J. Chen, Yize Wang, Yi Hu, Dun-Shan Yu, Xiaojie Xu, Xiaochuan Deng, Yunpeng Xing, Yi Wen, Zhiqiang Li, Xu Li, Bo Zhang, Wei Huang, Xuan Li
{"title":"2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Proceedings","authors":"Wei Cheng, Guangnan Zhou, Fanming Zeng, Yang Jiang, Lingli Jiang, Qing Wang, Hongyu Yu, Jin Wei, Han Xu, Ruiliang Xie, K. J. Chen, Yize Wang, Yi Hu, Dun-Shan Yu, Xiaojie Xu, Xiaochuan Deng, Yunpeng Xing, Yi Wen, Zhiqiang Li, Xu Li, Bo Zhang, Wei Huang, Xuan Li","doi":"10.1109/icsict49897.2020.9278348","DOIUrl":"https://doi.org/10.1109/icsict49897.2020.9278348","url":null,"abstract":"A Novel Shortest-distance Path-based Multicast Routing Algorithm for Network-on-Chips A Low-Power 16-Channel SiPM Readout Front-end with a Shared SAR ADC in 180 nm Studying the Reliability of Ge nFinFETs by the Normalized Input-referred Voltage Noise Interconnect Structures BEOL A Two-ASIC Front-End for MEMS Accelerometers A Photovoltaic and Thermal Energy Combining Harvesting Interface Circuit with MPPT and Single High Dynamic Range Pixel Circuit with High-voltage Protection for 128×128 Linear-mode APD high-efficiency WPT system with dual-output and enhanced coupling Study on Trapping HEMTs The Ultra-Wideband 0.5-15GHz LNA Reconfigurable Receiver System 28 nm A Ka-Band High-Gain and Wideband mmW Down-Conversion Mixer for 5G Communication Applications The Superjunction Device with Optimized Process Window of Breakdown Voltage low power readout circuit for 16-bit Speed DAC R2R An Impedance Calibration Method Based on Temperature and Process Monitor for High-Performance Bipolar GaN Diode Realized Broadened Quantum Well Three-Dimensional Enhancement-Type GaN HEMT High Power Transmission Capability Extended Well A decimation filter Sigma delta modulator FMCW transceiver","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"94 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83885006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Research on Secure JTAG Debugging Model Based on Schnorr Identity Authentication Protocol 基于Schnorr身份认证协议的JTAG安全调试模型研究
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278378
Wang Kai, Li Wei, Chen Tao, Nan Longmei
{"title":"Research on Secure JTAG Debugging Model Based on Schnorr Identity Authentication Protocol","authors":"Wang Kai, Li Wei, Chen Tao, Nan Longmei","doi":"10.1109/ICSICT49897.2020.9278378","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278378","url":null,"abstract":"As a general interface for chip system testing and on-chip debugging, JTAG is facing serious security threats. By analyzing the typical JTAG attack model and security protection measures, this paper designs a secure JTAG debugging model based on Schnorr identity authentication protocol, and takes RISCV as an example to build a set of SoC prototype system to complete functional verification. Experiments show that this secure JTAG debugging model has high security, flexible implementation, and good portability. It can meet the JTAG security protection requirements in various application scenarios. The maximum clock frequency can reach 833MHZ, while the hardware overhead is only 47.93KGate.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"42 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82630208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A VCO-Based Continuous Time Delta-sigma ADC with An Alternative Feedforward Scheme VCO 基于VCO的可选前馈方案的连续时间Delta-sigma ADC
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278289
Mengying Hu, Yuekang Guo, J. Jin
{"title":"A VCO-Based Continuous Time Delta-sigma ADC with An Alternative Feedforward Scheme VCO","authors":"Mengying Hu, Yuekang Guo, J. Jin","doi":"10.1109/ICSICT49897.2020.9278289","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278289","url":null,"abstract":"A Voltage Controlled Oscillator (VCO) based continuous-time Delta-Sigma analog-to-digital converter (ADC) with an alternative new feedforward VCO scheme contributing to higher oscillation frequency within VCO-Based quantizer is explored in this paper. Fourth-Order noise shaping is achieved using three operational transconductance amplifiers (OTAs) and VCO acting as integrator and quantizer. Meanwhile, the excess loop delay (ELD) introduced by the finite gain-bandwidth product of OTAs is compensated by zero-order path in the loop filter to reduce the power consumption further. The simulation results indicate that this prototype achieves a SNDR of 72.17 dB over 10MHz bandwidth sampling at 400MHz while consumes 24mW for a 1.8V supply in 180nm CMOS technology.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"13 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82890712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of RTN and Variability on RRAM-Based Neural Network RTN和变异对基于rram的神经网络的影响
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278290
P. Freitas, Z. Chai, W. Zhang, J. F. Zhang, J. Marsland
{"title":"Impact of RTN and Variability on RRAM-Based Neural Network","authors":"P. Freitas, Z. Chai, W. Zhang, J. F. Zhang, J. Marsland","doi":"10.1109/ICSICT49897.2020.9278290","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278290","url":null,"abstract":"Resistive switching memory devices can be categorized into filamentary RRAM or non-filamentary RRAM depending on the switching mechanisms. Both types of RRAM devices have been studied as novel synaptic devices in hardware neural networks. In this work, we analyze the amplitude of Random Telegraph Noise (RTN) and program-induced variabilities in both TaOx/Ta2Os filamentary and TiO2/a-Si (a-VMCO) non-filamentary RRAM devices and evaluate their impact on the pattern recognition accuracy of neural networks. It is revealed that the non-filamentary RRAM has a tighter RTN amplitude distribution than its filamentary counterpart, and also has much lower programed-induced variability, which lead to much smaller impact on the recognition accuracy, making it a promising candidate in synaptic application.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89583209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Complex Placement Region Handling Based on Electrostatic System Modeling 基于静电系统建模的复杂放置区域处理
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278229
Yongyi Guo, Yingjie Wu, Zhipeng Huang, Jianli Chen
{"title":"Complex Placement Region Handling Based on Electrostatic System Modeling","authors":"Yongyi Guo, Yingjie Wu, Zhipeng Huang, Jianli Chen","doi":"10.1109/ICSICT49897.2020.9278229","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278229","url":null,"abstract":"With the additional fence region constraints in modern circuit designs, the VLSI placement problem has become more complex and challenging. A placement solution without considering fence region constraints may cause many problems in the legalization stage and result in an inferior placement. In this paper, we present an effective placement region handling method based on the two-dimensional electrostatic system modeling. Under the fence region constrains, we first generate multiple density maps for assigning cells to their respective fence regions. Then, we further add proper fence filler nodes to each density map, which is able to squeeze fence cells to be placed closer. The placement performance is validated through experiments on ISPD 2015 benchmarks. Experimental results show that, compared with the state-of-the-art placer NTUplace4dr, our proposed method not only reduces the wirelength by 9.9% but also achieves 5x faster runtime.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"90 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89959767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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