2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)最新文献

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A Low-Power 16-Channel SiPM Readout Front-end with a Shared SAR ADC in 180 nm CMOS 低功耗16通道SiPM读出前端与共享SAR ADC在180纳米CMOS
Yuxuan Tang, Runxi Zhang, Jinghong Chen
{"title":"A Low-Power 16-Channel SiPM Readout Front-end with a Shared SAR ADC in 180 nm CMOS","authors":"Yuxuan Tang, Runxi Zhang, Jinghong Chen","doi":"10.1109/ICSICT49897.2020.9278142","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278142","url":null,"abstract":"This paper reports a low-power and high-timing resolution silicon photomultiplier (SiPM) readout front-end in a 180 nm CMOS technology. A low-input impedance current buffer employing current feedback is developed to achieve direct charge integration without the use of power-hungry charge-sensitive amplifiers (CSAs). A customized 10-bit SAR ADC is designed for energy digitization. The ADC is shared among 16 readout channels to reduce the chip area and improve power efficiency. The SAR ADC reuses the charge integration capacitor in each readout channel as the ADC sampling capacitor to further lower the power consumption. To reduce the SiPM noise-induced timing measurement error, an on-chip high-pass filter (HPF) based fast pulse generation approach is developed to sharpen the long-tailed SiPM current pulses into fast pulses. With a 1.8 V power supply, the SAR ADC consumes 743 µW at 16 MS/s, and achieves a SNDR of 56.48 dB and a SFDR of 62.53 dB. The on-chip fast pulse generation brings a 35 ps improvement in timing resolution without increasing the number of I/O pin counts. Including the front-end current buffer, current mirrors, charge integrator and the shared ADC, each channel of the readout system consumes 3.8 mW of power with a conversion period of 1 µs.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"36 6 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78012234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A 2.4GHz OOK Power Programmable CMOS RF Power Amplifier 一种2.4GHz OOK功率可编程CMOS射频功率放大器
Li-han Cui, Hejia Cai, Tao Wang, Zhi-liang Hong
{"title":"A 2.4GHz OOK Power Programmable CMOS RF Power Amplifier","authors":"Li-han Cui, Hejia Cai, Tao Wang, Zhi-liang Hong","doi":"10.1109/icsict49897.2020.9278369","DOIUrl":"https://doi.org/10.1109/icsict49897.2020.9278369","url":null,"abstract":"The post-simulation result of a power programmable 2.4GHz OOK radio frequency power amplifier (RF PA) is presented. It is implemented in 65nm CMOS process with 1.1V power supply. Its output power is programmable with digital setting channel width of the output power MOS transistors, meanwhile the output of the first stage can be digital controlled too. The simulation results of all output power levels from −23.01dBm to 8.92dBm are achieved.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"6 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76917783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Copyright notice 2020 IEEE第15届固态和集成电路技术国际会议(ICSICT) -版权声明
{"title":"2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) - Copyright notice","authors":"","doi":"10.1109/icsict49897.2020.9278335","DOIUrl":"https://doi.org/10.1109/icsict49897.2020.9278335","url":null,"abstract":"","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"4 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80188536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Real-Time 2.4-GHz Doppler Radar System with All Functionalities on Board for Vital Signal Detection 实时2.4 ghz多普勒雷达系统,具有机载生命信号检测的所有功能
Wei Ma, Zhiming Xiao, Dongyang Tang, Fei Liu, Weibo Hu
{"title":"A Real-Time 2.4-GHz Doppler Radar System with All Functionalities on Board for Vital Signal Detection","authors":"Wei Ma, Zhiming Xiao, Dongyang Tang, Fei Liu, Weibo Hu","doi":"10.1109/ICSICT49897.2020.9278303","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278303","url":null,"abstract":"The protype of a 2.4-GHz zero-IF Doppler radar system with all functionalities on board for real-time vital sign detection is implemented and presented in this paper. The radar system accomplishes RF front end, base-band analog processing, analog-to-digital conversion, digital signal processing for the vital-sign signal extraction and the numeric and graphic result display. In the system, a Sallen-Key filter and a FPGA development board are used to remove interferences, adjust gain, and collect and process raw data. Experiments show that the respiration and heartbeat can be clearly detected when a person sitting at 1 meter away from the proposed radar. Both the realtime waveform and spectrum analysis are displayed on a separate LCD through an VGA interface.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"20 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82409793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Photovoltaic and Thermal Energy Combining Harvesting Interface Circuit with MPPT and Single Inductor 一种基于MPPT和单电感的光电与热能结合采集接口电路
Peichao Zhang, Lianxi Liu
{"title":"A Photovoltaic and Thermal Energy Combining Harvesting Interface Circuit with MPPT and Single Inductor","authors":"Peichao Zhang, Lianxi Liu","doi":"10.1109/ICSICT49897.2020.9278256","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278256","url":null,"abstract":"This paper proposed a photovoltaic and thermal energy combining harvesting interface circuit. The time-multiplexed operating of the power stage circuit can harvest thermal energy and photovoltaic energy simultaneously in a cycle, obtaining high efficiency and a smaller volume of the system. Combined with the open-circuit voltage algorithm, the interface circuit outputs energy at the maximum power point. The proposed interface circuit is implemented in a 0.18 µm standard CMOS process. The simulation results show that the conduction time of the thermal energy path occupies about 50% of the cycle and the conduction time of the photovoltaic energy path occupies about 5% of the cycle. The peak tracking efficiency of photovoltaic energy is 99.1 % and the peak tracking efficiency of thermal energy is 99%. The peak power conversion efficiency of the overall circuit is 89%.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"5 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80070142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Research on Secure JTAG Debugging Model Based on Schnorr Identity Authentication Protocol 基于Schnorr身份认证协议的JTAG安全调试模型研究
Wang Kai, Li Wei, Chen Tao, Nan Longmei
{"title":"Research on Secure JTAG Debugging Model Based on Schnorr Identity Authentication Protocol","authors":"Wang Kai, Li Wei, Chen Tao, Nan Longmei","doi":"10.1109/ICSICT49897.2020.9278378","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278378","url":null,"abstract":"As a general interface for chip system testing and on-chip debugging, JTAG is facing serious security threats. By analyzing the typical JTAG attack model and security protection measures, this paper designs a secure JTAG debugging model based on Schnorr identity authentication protocol, and takes RISCV as an example to build a set of SoC prototype system to complete functional verification. Experiments show that this secure JTAG debugging model has high security, flexible implementation, and good portability. It can meet the JTAG security protection requirements in various application scenarios. The maximum clock frequency can reach 833MHZ, while the hardware overhead is only 47.93KGate.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"42 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82630208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A wideband transimpedance amplifier with tee network topology 一种具有tee网络拓扑结构的宽带跨阻放大器
Rui Yang, Shaowei Zhen, Y. Zhang, Yi-Qiang Zhao, Xiao Yang, Bo Zhang
{"title":"A wideband transimpedance amplifier with tee network topology","authors":"Rui Yang, Shaowei Zhen, Y. Zhang, Yi-Qiang Zhao, Xiao Yang, Bo Zhang","doi":"10.1109/ICSICT49897.2020.9278244","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278244","url":null,"abstract":"In this paper, a wideband transimpedance amplifier (TIA) was proposed for high speed optical receiver chips. The proposed TIA replaces feedback resistance in conventional design with a kind of tee network circuit. Consequently, the bandwidth (BW) and phase margin (PM) of TIA are enhanced significantly. Besides, cascade current mirror was also used for improving power supply rejection ratio (PSRR). This wideband TIA was designed in standard 0.35 CMOS technology. Simulation results show that the proposed TIA has a bandwidth of 145 MHz, low frequency transimpedance gain of 93 $mathrm{dB}Omega$, phase margin of more than 66° and low frequency power supply rejection ratio (PSRR) of $-157dB$. And the average input referred noise current spectral density is 6. $8mathrm{pA}/sqrt{mathrm{H}mathrm{Z}}$ from DC to 500 MHz. The TIA we designed dissipates only 3.5 $mathrm{mW}$ with a 3.3 V power supply.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"15 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82541777","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
An SEU (Single-event Upset) Mitigation Strategy on Read-Write Separation SRAM Cell for Low Power Consumption 低功耗读写分离SRAM单元的SEU(单事件干扰)缓解策略
Zexin Su, Bo Li, Xiaohui Su, Fanyu Liu, Zhengsheng Han, Xinyu Liu, Konstantin O. Pctrosyants, I. Kharitonov
{"title":"An SEU (Single-event Upset) Mitigation Strategy on Read-Write Separation SRAM Cell for Low Power Consumption","authors":"Zexin Su, Bo Li, Xiaohui Su, Fanyu Liu, Zhengsheng Han, Xinyu Liu, Konstantin O. Pctrosyants, I. Kharitonov","doi":"10.1109/ICSICT49897.2020.9278325","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278325","url":null,"abstract":"SRAM for space applications continues to be disturbed by highly energetic charged particles along with technology node scaling, that is the single-event upset (SEU) in terms of time perspective. A 14T read-write separation SRAM cell in low power mode is proposed using radiation hardened by design (RHBD) technique, not only robust to SEU but also retaining the same performance as the 8T counterpart. The simulation results verify that the 14T SRAM cell is immune to single-point upsets and improves tolerance towards double-point upsets.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87836702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Impact of RTN and Variability on RRAM-Based Neural Network RTN和变异对基于rram的神经网络的影响
P. Freitas, Z. Chai, W. Zhang, J. F. Zhang, J. Marsland
{"title":"Impact of RTN and Variability on RRAM-Based Neural Network","authors":"P. Freitas, Z. Chai, W. Zhang, J. F. Zhang, J. Marsland","doi":"10.1109/ICSICT49897.2020.9278290","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278290","url":null,"abstract":"Resistive switching memory devices can be categorized into filamentary RRAM or non-filamentary RRAM depending on the switching mechanisms. Both types of RRAM devices have been studied as novel synaptic devices in hardware neural networks. In this work, we analyze the amplitude of Random Telegraph Noise (RTN) and program-induced variabilities in both TaOx/Ta2Os filamentary and TiO2/a-Si (a-VMCO) non-filamentary RRAM devices and evaluate their impact on the pattern recognition accuracy of neural networks. It is revealed that the non-filamentary RRAM has a tighter RTN amplitude distribution than its filamentary counterpart, and also has much lower programed-induced variability, which lead to much smaller impact on the recognition accuracy, making it a promising candidate in synaptic application.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"2 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89583209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Memory Modeling with Dynamic Time Evolution Method for Neuromorphic Circuit Simulations 基于动态时间演化方法的神经形态电路记忆建模
Xiaoqing Huang, Xuhui Chen, Huifang Hu, Haotian Zhong, Lining Zhang, M. Chan, Ru Huang
{"title":"Memory Modeling with Dynamic Time Evolution Method for Neuromorphic Circuit Simulations","authors":"Xiaoqing Huang, Xuhui Chen, Huifang Hu, Haotian Zhong, Lining Zhang, M. Chan, Ru Huang","doi":"10.1109/icsict49897.2020.9278379","DOIUrl":"https://doi.org/10.1109/icsict49897.2020.9278379","url":null,"abstract":"For simulations of emerging neuromorphic circuits an analog memory modeling strategy with the dynamic time evolution method (DTEM) is reported. Dynamic state variables are needed to trace the physical quantities of the memory state representations. In a SPICE simulator time varying nodal voltages of the transient domain are capable to emulate changings of these physical quantities thus leveraging sub-circuits (SC) with additional nodes is one feasible method. To accommodate large scale simulation of neuromorphic circuits, the dynamic time evolution method is proposed to trace the varying memory states in the spiking-time-dependent-plasticity (STDP). Circuit matrix size is reduced with the DTEM implementations thus efficient simulation speedups are achieved.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89114058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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