发布求助
文献互助 智能选刊 最新文献

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)最新文献

筛选
英文 中文
A dual-gate IGZO Source-Gated transistor based on field modulation by TCAD simulation 基于场调制的双栅极IGZO源门控晶体管的TCAD仿真
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278220
Ning Li, Zhao Rong, Lining Zhang, Min Zhang
{"title":"A dual-gate IGZO Source-Gated transistor based on field modulation by TCAD simulation","authors":"Ning Li, Zhao Rong, Lining Zhang, Min Zhang","doi":"10.1109/ICSICT49897.2020.9278220","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278220","url":null,"abstract":"In this work, a configurable indium-gallium-zinc-oxide source-gated transistors (SGT) is proposed based on the field modulation of schottky contacts. The device concept is evaluated through TCAD numerical device simulations and related parameters are discussed. The results show that the SGT device can be achieved by voltage regulation of two gates, the channel modulation gate and contact modulation gate, and that its saturation voltage and current are under a significant modulation within a wide range. While designs with metal engineering may suffer from Fermi level pinning, the proposed device provides an alternative method for design optimizations of SGT for their applications in low-power active-display circuits.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"26 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91190744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Physical and Electrical Characterization of Doped Amorphous Silicon Resistor 掺杂非晶硅电阻器的物理和电学特性
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278180
Xiaolan Zhong, Xiaoxu Kang, Ruoxi Shen
{"title":"Physical and Electrical Characterization of Doped Amorphous Silicon Resistor","authors":"Xiaolan Zhong, Xiaoxu Kang, Ruoxi Shen","doi":"10.1109/ICSICT49897.2020.9278180","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278180","url":null,"abstract":"Amorphous Silicon (Si) is widely used in CMOS technology, and now applications can be found in MEMs/Sensor products because of its remarkable performance. In this paper, low temperature PECVD amorphous Si process was developed at 200mm CMOS BEOL with low stress at about -30MPa (compressive mode), and there is no peeling or crack problem for the film deposition. Good thickness and sheet resistance uniformity can be achieved of the amorphous Si film. Its thickness uniformity can reach 0.56%, and Rs uniformity can reach 1.22%. Then it was used to fabricate sensing resistor for temperature sensor application, which was defined by thin TiTiN metal layer pattern. To achieve good contact performance, Ar plasma etching process was introduced before metal layer deposition, and its etch rate can be well controlled. From the IV curve, it can be seen that good ohmic contact can be achieved. High selectivity thin metal layer etching process was developed with no process damage to amorphous Si, and 49 point resistance uniformity within wafer can be controlled to less than 2%. Thermal coefficient of resistance (TCR) was measured from 25°C to 40°C, and TCR value can reach at about 1.88%. 1/f Noise performance was evaluated for the resistor, and 1/f noise power at 100Hz can be controlled to -148dB. The measured data of doped amorphous Si resistor can well meet requirements of temperature based sensor.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"94 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73069752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Micromachined Multimodal Probe Technology for Ischemia Muscle Monitoring 用于缺血肌肉监测的微机械多模态探针技术
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278140
Y. T. Cheng, Y. S. Chen
{"title":"A Micromachined Multimodal Probe Technology for Ischemia Muscle Monitoring","authors":"Y. T. Cheng, Y. S. Chen","doi":"10.1109/ICSICT49897.2020.9278140","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278140","url":null,"abstract":"In this paper, we present a micromachined multimodal probe technology for ischemia muscle monitoring. It is a platform technology to fabricate silicon sensing probes with the characteristics of low-cost, multifunction, and small form factor, which can detect temperature, pH value, and the concentration of K+, NH4+, etc. inside muscle tissue suitable for peripheral arterial occlusive disease detection and intraoperative heart muscle monitoring, respectively. From animal experiments, the micromachined probe has shown its potential to provide physicians a multi-mode diagnosis with corresponding real-time medical treatment feedback.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"15 1","pages":"1-5"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73023875","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Progress of Lead-Free Halide Perovskite X-ray Detectors 无铅卤化物钙钛矿x射线探测器的研究进展
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278179
Hainan Zhang, Guanhua Dun, Y. Qiao, D. Xie, T. Ren
{"title":"Progress of Lead-Free Halide Perovskite X-ray Detectors","authors":"Hainan Zhang, Guanhua Dun, Y. Qiao, D. Xie, T. Ren","doi":"10.1109/ICSICT49897.2020.9278179","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278179","url":null,"abstract":"Lead halide perovskite for radiation detection still faces significant challenges despite its exciting progress. The main issues which hinder further development are the toxicity problem of lead and the intrinsic instability for volatile organic parts in lead-based perovskites. Therefore, searching for low-toxic and intrinsically stable perovskite materials have drawn a great attention from the public. In this review, lead-free perovskites are divided into two types: double perovskites type as A2MIMIIX6 and low-dimensional perovskites type as A3W2X9. The synthesis methods of these lead-free perovskites are discussed and the performance on X-ray detection are accordingly summarized. Moreover, a brief outlook on the future development of lead-free perovskites in radiation detection is proposed.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"22 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73785329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A CMOS Ka-Band Wireless Transceiver for Future Non-Terrestrial 6G Networks 面向未来非地面6G网络的CMOS ka波段无线收发器
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278199
A. Shirane, Yun Wang, K. Okada
{"title":"A CMOS Ka-Band Wireless Transceiver for Future Non-Terrestrial 6G Networks","authors":"A. Shirane, Yun Wang, K. Okada","doi":"10.1109/ICSICT49897.2020.9278199","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278199","url":null,"abstract":"This paper introduces a wireless transceiver fabricated with a standard Si CMOS process for a Ka-band satellite communication. For the increasing demand for the high speed and low-cost satellite communication terminals, the presented transceiver IC contributes to the reduction of the number of components, PCB footprints, and power consumption. The transceiver exploits a direct-conversion architecture and consists of two paths multi-mode receiver and one path high linearity transmitter. The integrated two receiver paths enable the polarization and frequency multiplexing to enhance the data rate. The transceiver can operate in the frequency range of the Ka-band satellite communication with higher integration level and lower power consumption compared with the conventional Ka-band wireless transceivers.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"88 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74025774","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
The Ultra-Wideband 0.5-15GHz LNA for Reconfigurable Receiver System in 28 nm CMOS 用于可重构接收系统的超宽带0.5-15GHz LNA
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278188
Zhenhua Hu, Maliang Liu, R. Ding, Zhang‐ming Zhu, Yin-tang Yang
{"title":"The Ultra-Wideband 0.5-15GHz LNA for Reconfigurable Receiver System in 28 nm CMOS","authors":"Zhenhua Hu, Maliang Liu, R. Ding, Zhang‐ming Zhu, Yin-tang Yang","doi":"10.1109/ICSICT49897.2020.9278188","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278188","url":null,"abstract":"A 0.5-8GHz LNA and an 8-15GHz LNA connected by the active switch used in the Ultra-Wideband (UWB) reconfigurable receiver are presented in this paper. The common drain stage and resistance negative feedback technology as well as the source degeneration inductive technology are introduced to achieve a high flat gain and fine input matching. The current-reused technique is adopted to improve the gain and the noise characteristics. The 0.5-8GHz LNA I achieves a high flat gain of 22.32-24.56 dB, a noise figure (NF) of 3.69-4.52 dB and the S11 batter than -10.78 dB across the band. The 8-15GHz LNA II achieves a high flat gain of 24.3-26.59 dB, a NF of 3.80-4.51 dB and the S11 batter than -12.56 dB in the frequency band.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"50 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73556732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Detailed Routing Short Violations Prediction Method Using Graph Convolutional Network 基于图卷积网络的详细路由短违规预测方法
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278302
Xuan Chen, Zhixiong Di, Wei Wu, Quanyuan Feng, Jiang-Yi Shi
{"title":"Detailed Routing Short Violations Prediction Method Using Graph Convolutional Network","authors":"Xuan Chen, Zhixiong Di, Wei Wu, Quanyuan Feng, Jiang-Yi Shi","doi":"10.1109/ICSICT49897.2020.9278302","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278302","url":null,"abstract":"With the continuous shrink of IC manufacturing process, how to accurately predict the routing violations before detailed routing is becoming more and more important to improve the placement quality. In this paper, we propose a detailed routing short violations prediction model based on the Graph Convolutional Network (GCN). Based on the key features extracted from the placement and detailed routing stage separately, we train a GCN model to build a map relationship between these two stages. Through this model, we can predict the detailed routing short violations at placement stage successfully. Experiments show that the average prediction accuracy of our model is 94% which is higher than existing method based on machine learning.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"49 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74664167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Novel Page-Forming Scheme with Ultra-Low Bit-Error-Rate and High Reliability on a 1Mb RRAM Chip 一种基于1Mb RRAM芯片的超低误码率和高可靠性的页面形成方案
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278288
Junyi Wang, L. Pan, B. Gao, Dabin Wu, Jianshi Tang, Huaqiang Wu, H. Qian
{"title":"A Novel Page-Forming Scheme with Ultra-Low Bit-Error-Rate and High Reliability on a 1Mb RRAM Chip","authors":"Junyi Wang, L. Pan, B. Gao, Dabin Wu, Jianshi Tang, Huaqiang Wu, H. Qian","doi":"10.1109/ICSICT49897.2020.9278288","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278288","url":null,"abstract":"RRAM is regarded as one of the emerging storage class memory, but the reliability and variability issues still need to be improved. In this work, two-transistors-tow-resistors (2T2R) cell structure and several peripheral circuits are developed, improving the bit-error-rate (BER) significantly. Conventional forming process of RRAM is time consuming, it is another critical issue that should be overcome before mass production. This work proposes a novel flash forming scheme on a specific designed RRAM array. With this verification-free scheme, a page of RRAM cells can be formed simultaneously, reducing the time of forming by orders of magnitude. A 1Mb full chip is designed and fabricated based on the proposed scheme, an ultra-low BER of ~ 10−5 without any error-correction is achieved. Fast speed (<10ns), excellent chip-to-chip uniformity and reliability (>106 cycles, > 10 years@25°C) are also demonstrated on the chip level.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"6 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74577825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Variation Investigation of Junction-less Transistor with Side-wall Charge-plasma Structure Induced by Line Edge Roughness 线边缘粗糙度诱导无结边壁电荷等离子体结构晶体管的变化研究
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278349
Kai Liu, Hung-Chih Chin, H. Lou, Kuan‐Chang Chang, Xinnan Lin
{"title":"Variation Investigation of Junction-less Transistor with Side-wall Charge-plasma Structure Induced by Line Edge Roughness","authors":"Kai Liu, Hung-Chih Chin, H. Lou, Kuan‐Chang Chang, Xinnan Lin","doi":"10.1109/ICSICT49897.2020.9278349","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278349","url":null,"abstract":"In this work, the fluctuations of the electrical characteristics including ON -current, OFF -current, subthreshold swing and threshold voltage, due to line edge roughness (LER) for double-gate charge-plasma junctionless transistor (CPJLT) and side-wall charge-plasma junctionless transistor (S-CPJLT) are explored. Results shows that S-CPJLT has less fluctuations in ON -current while maintaining similar performance of other electrical characteristics. Besides, S-CPJLT has larger ON-current, smaller OFF-current on average. This work indicates that S-CPJLT has greater potential in electronic device development.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"38 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76463279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Superjunction Device with Optimized Process Window of Breakdown Voltage 具有优化击穿电压过程窗口的超结器件
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278209
M. Ren, Lv-Qiang Li, Yaoyao Lan, Rongyao Ma, Xin Zhang, Fang Zheng, Wei Gao, Ze-hong Li, Bo Zhang
{"title":"The Superjunction Device with Optimized Process Window of Breakdown Voltage","authors":"M. Ren, Lv-Qiang Li, Yaoyao Lan, Rongyao Ma, Xin Zhang, Fang Zheng, Wei Gao, Ze-hong Li, Bo Zhang","doi":"10.1109/ICSICT49897.2020.9278209","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278209","url":null,"abstract":"In order to improve the process window of breakdown voltage (BV), a vertical variable doping (VVD) superjunction MOSFET (SJ-MOS) is proposed. The charge superposition principle is used to analyze the change of electric field (e- field) caused by the gradient doping of pillars. Compared with the uniform doping SJ-MOS, it is shown that the negative doping gradient in P-pillar and the positive doping gradient in N-pillar can make the distribution of e- field more uniform, which is beneficial to the expansion of the BV process window.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"19 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76615358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信