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2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)最新文献

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A dual-gate IGZO Source-Gated transistor based on field modulation by TCAD simulation 基于场调制的双栅极IGZO源门控晶体管的TCAD仿真
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278220
Ning Li, Zhao Rong, Lining Zhang, Min Zhang
{"title":"A dual-gate IGZO Source-Gated transistor based on field modulation by TCAD simulation","authors":"Ning Li, Zhao Rong, Lining Zhang, Min Zhang","doi":"10.1109/ICSICT49897.2020.9278220","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278220","url":null,"abstract":"In this work, a configurable indium-gallium-zinc-oxide source-gated transistors (SGT) is proposed based on the field modulation of schottky contacts. The device concept is evaluated through TCAD numerical device simulations and related parameters are discussed. The results show that the SGT device can be achieved by voltage regulation of two gates, the channel modulation gate and contact modulation gate, and that its saturation voltage and current are under a significant modulation within a wide range. While designs with metal engineering may suffer from Fermi level pinning, the proposed device provides an alternative method for design optimizations of SGT for their applications in low-power active-display circuits.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"26 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91190744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Ultra-Wideband 0.5-15GHz LNA for Reconfigurable Receiver System in 28 nm CMOS 用于可重构接收系统的超宽带0.5-15GHz LNA
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278188
Zhenhua Hu, Maliang Liu, R. Ding, Zhang‐ming Zhu, Yin-tang Yang
{"title":"The Ultra-Wideband 0.5-15GHz LNA for Reconfigurable Receiver System in 28 nm CMOS","authors":"Zhenhua Hu, Maliang Liu, R. Ding, Zhang‐ming Zhu, Yin-tang Yang","doi":"10.1109/ICSICT49897.2020.9278188","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278188","url":null,"abstract":"A 0.5-8GHz LNA and an 8-15GHz LNA connected by the active switch used in the Ultra-Wideband (UWB) reconfigurable receiver are presented in this paper. The common drain stage and resistance negative feedback technology as well as the source degeneration inductive technology are introduced to achieve a high flat gain and fine input matching. The current-reused technique is adopted to improve the gain and the noise characteristics. The 0.5-8GHz LNA I achieves a high flat gain of 22.32-24.56 dB, a noise figure (NF) of 3.69-4.52 dB and the S11 batter than -10.78 dB across the band. The 8-15GHz LNA II achieves a high flat gain of 24.3-26.59 dB, a NF of 3.80-4.51 dB and the S11 batter than -12.56 dB in the frequency band.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"50 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73556732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design and Comparison of FIR Filter Based on DSP Builder and HDL Coder 基于DSP Builder和HDL编码器的FIR滤波器设计与比较
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278259
Qin Huang, Zilin Wang
{"title":"Design and Comparison of FIR Filter Based on DSP Builder and HDL Coder","authors":"Qin Huang, Zilin Wang","doi":"10.1109/ICSICT49897.2020.9278259","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278259","url":null,"abstract":"DSP Builder and HDL Coder are common VHDL /Verilog code generation tools, but the comparison of the two tools has not been fully explored. In this paper, an FIR filter with the same structure, word length and filter coefficients is built, and Verilog code is generated by using the above two tools respectively. Then, we compare the resource consumption in Quartus II. The results show that DSP Builder has advantages in the consumption of pins, and HDL Coder has advantages in the consumption of logic elements. This guides us to select specific code generation tools according to the actual needs.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"112 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88804667","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Memory Modeling with Dynamic Time Evolution Method for Neuromorphic Circuit Simulations 基于动态时间演化方法的神经形态电路记忆建模
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/icsict49897.2020.9278379
Xiaoqing Huang, Xuhui Chen, Huifang Hu, Haotian Zhong, Lining Zhang, M. Chan, Ru Huang
{"title":"Memory Modeling with Dynamic Time Evolution Method for Neuromorphic Circuit Simulations","authors":"Xiaoqing Huang, Xuhui Chen, Huifang Hu, Haotian Zhong, Lining Zhang, M. Chan, Ru Huang","doi":"10.1109/icsict49897.2020.9278379","DOIUrl":"https://doi.org/10.1109/icsict49897.2020.9278379","url":null,"abstract":"For simulations of emerging neuromorphic circuits an analog memory modeling strategy with the dynamic time evolution method (DTEM) is reported. Dynamic state variables are needed to trace the physical quantities of the memory state representations. In a SPICE simulator time varying nodal voltages of the transient domain are capable to emulate changings of these physical quantities thus leveraging sub-circuits (SC) with additional nodes is one feasible method. To accommodate large scale simulation of neuromorphic circuits, the dynamic time evolution method is proposed to trace the varying memory states in the spiking-time-dependent-plasticity (STDP). Circuit matrix size is reduced with the DTEM implementations thus efficient simulation speedups are achieved.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89114058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Proceedings 2020 IEEE第十五届固态与集成电路技术国际会议论文集
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/icsict49897.2020.9278283
Shao-Wei Yu, Xiaona Zhu, T. Tang
{"title":"2020 IEEE 15th International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Proceedings","authors":"Shao-Wei Yu, Xiaona Zhu, T. Tang","doi":"10.1109/icsict49897.2020.9278283","DOIUrl":"https://doi.org/10.1109/icsict49897.2020.9278283","url":null,"abstract":"","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"8 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90644984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Implementation of Convolutional Neural Network with Co-design of High-Level Synthesis and Verilog HDL 高阶合成与Verilog HDL协同设计卷积神经网络的实现
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278149
Hejie Yu, Jun Cheng, X. Zhang, Yuzhe Gao, K. Mei
{"title":"Implementation of Convolutional Neural Network with Co-design of High-Level Synthesis and Verilog HDL","authors":"Hejie Yu, Jun Cheng, X. Zhang, Yuzhe Gao, K. Mei","doi":"10.1109/ICSICT49897.2020.9278149","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278149","url":null,"abstract":"In recent years, Convolutional Neural Networks(CNNs) have been widely adopted for image classification and target recognition. As one of CNN's main hardware implementation platforms, FPGA has its advantages of high flexibility, excellent trade-off between performance and power, but still has the problems of complex developing processes and poor adaptability for various algorithm models. Therefore, a high-performance and fast hardware implementation architecture adaptation to the CNNs is presented in the paper. The hardware architecture is designed with co-design of High-Level Synthesis(HLS) and Verilog HDL, which simplifies the design process and ensures performance. And it adopts the variables parameterization to deal with the problem of pool model adaptability. With row-by-row calculation, the circuits adopt the layered parallelism to ensure the flexibility of convolution and the pipeline parallel calculation to improve the speed. The paper achieves an overall average 359.7GOP/s for the AlexNet on Xilinx ZCU104 platform.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"10 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87309421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An SEU (Single-event Upset) Mitigation Strategy on Read-Write Separation SRAM Cell for Low Power Consumption 低功耗读写分离SRAM单元的SEU(单事件干扰)缓解策略
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278325
Zexin Su, Bo Li, Xiaohui Su, Fanyu Liu, Zhengsheng Han, Xinyu Liu, Konstantin O. Pctrosyants, I. Kharitonov
{"title":"An SEU (Single-event Upset) Mitigation Strategy on Read-Write Separation SRAM Cell for Low Power Consumption","authors":"Zexin Su, Bo Li, Xiaohui Su, Fanyu Liu, Zhengsheng Han, Xinyu Liu, Konstantin O. Pctrosyants, I. Kharitonov","doi":"10.1109/ICSICT49897.2020.9278325","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278325","url":null,"abstract":"SRAM for space applications continues to be disturbed by highly energetic charged particles along with technology node scaling, that is the single-event upset (SEU) in terms of time perspective. A 14T read-write separation SRAM cell in low power mode is proposed using radiation hardened by design (RHBD) technique, not only robust to SEU but also retaining the same performance as the 8T counterpart. The simulation results verify that the 14T SRAM cell is immune to single-point upsets and improves tolerance towards double-point upsets.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87836702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A novel SOI-based ridge waveguide SiGe Heterojunction Phototransistor 一种新型soi基脊波导SiGe异质结光电晶体管
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278192
Ce Bian, Hongyun Xie, M. Guo, Yin Sha, Yang Xiang, X. Liu, Wanrong Zhang
{"title":"A novel SOI-based ridge waveguide SiGe Heterojunction Phototransistor","authors":"Ce Bian, Hongyun Xie, M. Guo, Yin Sha, Yang Xiang, X. Liu, Wanrong Zhang","doi":"10.1109/ICSICT49897.2020.9278192","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278192","url":null,"abstract":"A kind of SiGe heterojunction phototransistor with gradual coupled ridge waveguide based on silicon-on-insulator (SOI SiGe GRC HPT) is designed and optimized to improve its optical responsivity and working speed. When the width and length of the ridge waveguide are optimized as 3um and 20um separately, the ridge waveguide based on SOI provide the same limitation for TE mode and TM mode and the suitable propagation path for incident light. The maximum characteristic frequency of SOI SiGe GRC HPT is 102GHz, its saturation current is 20mA and its optical responsivity is 0.5 A/W.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"38 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84042912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 28GHz 6-bit Two-stage Vector-sum Phase Shifter with Low RMS Error for 5G Mobile Communication 5G移动通信用低有效值误差的28GHz 6位两级矢量和移相器
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278260
Xingyu Qi, Shuyu Liu, Zongyuan Zheng, Bo Wang, Xing Zhang
{"title":"A 28GHz 6-bit Two-stage Vector-sum Phase Shifter with Low RMS Error for 5G Mobile Communication","authors":"Xingyu Qi, Shuyu Liu, Zongyuan Zheng, Bo Wang, Xing Zhang","doi":"10.1109/ICSICT49897.2020.9278260","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278260","url":null,"abstract":"This paper presents a 28GHz 6-bit active phase shifter in 65nm CMOS for 5G mobile communication. To lower the RMS error, a novel two-stage vector-sum architecture is proposed, which divides the 6-bit phase shifter into four 4-bit sub phase shifters and one active vector combiner. The 4-bit sub phase shifters are implemented just by switches and differential gain units which can also lower the RMS error apparently. Through the optimization of circuit topologies, the RMS error of the phase shifter is significantly lowered. The 6-bit phase shifter results in a simulated RMS gain error of 0.21dB and RMS phase error of 1.2° between 27.5-28.35GHz. The total current consumption is 11.8mA from a 1.2V supply voltage and the core size is 0.86×0.85mm2.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"14 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84428816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Digital Synthesizable Full Common-mode Input Range Dynamic Voltage Comparator 一种数字合成全共模输入范围动态电压比较器
2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT) Pub Date : 2020-11-03 DOI: 10.1109/ICSICT49897.2020.9278145
Min Li, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng
{"title":"A Digital Synthesizable Full Common-mode Input Range Dynamic Voltage Comparator","authors":"Min Li, Jue Wang, Xu Cheng, Jun Han, Xiaoyang Zeng","doi":"10.1109/ICSICT49897.2020.9278145","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278145","url":null,"abstract":"This paper presents a digital synthesizable full common-mode input range dynamic voltage comparator (FCMRDVC). It is a modified version of the rail-to-rail dynamic voltage comparator (RRDVC), with a view to a real rail-to-rail common-mode input range (CMR). The proposed FCMRDVC is designed and synthesized in 28-nm CMOS technology with the active area of 43.2µm2, and the simulation results show the maximum power consumption of 7.5nW under 0.3V power supply voltage (VDD) and CMR of 0-VDD.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"32 11 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88384711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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