A 28GHz 6-bit Two-stage Vector-sum Phase Shifter with Low RMS Error for 5G Mobile Communication

Abstract

This paper presents a 28GHz 6-bit active phase shifter in 65nm CMOS for 5G mobile communication. To lower the RMS error, a novel two-stage vector-sum architecture is proposed, which divides the 6-bit phase shifter into four 4-bit sub phase shifters and one active vector combiner. The 4-bit sub phase shifters are implemented just by switches and differential gain units which can also lower the RMS error apparently. Through the optimization of circuit topologies, the RMS error of the phase shifter is significantly lowered. The 6-bit phase shifter results in a simulated RMS gain error of 0.21dB and RMS phase error of 1.2° between 27.5-28.35GHz. The total current consumption is 11.8mA from a 1.2V supply voltage and the core size is 0.86×0.85mm2.