{"title":"基于VCO的可选前馈方案的连续时间Delta-sigma ADC","authors":"Mengying Hu, Yuekang Guo, J. Jin","doi":"10.1109/ICSICT49897.2020.9278289","DOIUrl":null,"url":null,"abstract":"A Voltage Controlled Oscillator (VCO) based continuous-time Delta-Sigma analog-to-digital converter (ADC) with an alternative new feedforward VCO scheme contributing to higher oscillation frequency within VCO-Based quantizer is explored in this paper. Fourth-Order noise shaping is achieved using three operational transconductance amplifiers (OTAs) and VCO acting as integrator and quantizer. Meanwhile, the excess loop delay (ELD) introduced by the finite gain-bandwidth product of OTAs is compensated by zero-order path in the loop filter to reduce the power consumption further. The simulation results indicate that this prototype achieves a SNDR of 72.17 dB over 10MHz bandwidth sampling at 400MHz while consumes 24mW for a 1.8V supply in 180nm CMOS technology.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"13 1","pages":"1-3"},"PeriodicalIF":0.0000,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A VCO-Based Continuous Time Delta-sigma ADC with An Alternative Feedforward Scheme VCO\",\"authors\":\"Mengying Hu, Yuekang Guo, J. Jin\",\"doi\":\"10.1109/ICSICT49897.2020.9278289\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Voltage Controlled Oscillator (VCO) based continuous-time Delta-Sigma analog-to-digital converter (ADC) with an alternative new feedforward VCO scheme contributing to higher oscillation frequency within VCO-Based quantizer is explored in this paper. Fourth-Order noise shaping is achieved using three operational transconductance amplifiers (OTAs) and VCO acting as integrator and quantizer. Meanwhile, the excess loop delay (ELD) introduced by the finite gain-bandwidth product of OTAs is compensated by zero-order path in the loop filter to reduce the power consumption further. The simulation results indicate that this prototype achieves a SNDR of 72.17 dB over 10MHz bandwidth sampling at 400MHz while consumes 24mW for a 1.8V supply in 180nm CMOS technology.\",\"PeriodicalId\":6727,\"journal\":{\"name\":\"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)\",\"volume\":\"13 1\",\"pages\":\"1-3\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-11-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT49897.2020.9278289\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT49897.2020.9278289","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A VCO-Based Continuous Time Delta-sigma ADC with An Alternative Feedforward Scheme VCO
A Voltage Controlled Oscillator (VCO) based continuous-time Delta-Sigma analog-to-digital converter (ADC) with an alternative new feedforward VCO scheme contributing to higher oscillation frequency within VCO-Based quantizer is explored in this paper. Fourth-Order noise shaping is achieved using three operational transconductance amplifiers (OTAs) and VCO acting as integrator and quantizer. Meanwhile, the excess loop delay (ELD) introduced by the finite gain-bandwidth product of OTAs is compensated by zero-order path in the loop filter to reduce the power consumption further. The simulation results indicate that this prototype achieves a SNDR of 72.17 dB over 10MHz bandwidth sampling at 400MHz while consumes 24mW for a 1.8V supply in 180nm CMOS technology.