{"title":"A Low Noise Precision Operational Amplifier","authors":"Chenghe Wang, Liang Guo, Yuanjie Zhou","doi":"10.1109/ICSICT49897.2020.9278366","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278366","url":null,"abstract":"A low noise precision operational amplifier is presented in this paper, which has the advantages of low offset and low noise for high precision, high resolution and low error applications. The design was fabricated with a 40V bipolar process. The input stage of the circuit is a resistive load differential pair with an input bias current compensation structure. The second stage is a common-emitter structure in the middle. The output stage is complementary push-pull structure. When power supply is ±15V, measured results show that slew rate of the OPA is 0.3V/μs, it gets an open loop gain of 132dB with a supply current of 1.7mA and an input bias current of 2nA, the equivalent input noise is only 8nV/ √ Hz, and the area is about 2.3mm×1.6mm.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"13 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78461054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Ping-Pong Operated Inverter-based OTA using Correlated Level Shifting Technique","authors":"Tianqiao Wu, Z. Tan, N. Xie, Hao Zhang, Le Ye","doi":"10.1109/ICSICT49897.2020.9278332","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278332","url":null,"abstract":"This paper presents an inverter-based operational transconductance amplifier (OTA) which obtains high loop gain by correlated level shifting (CLS) technique with ping-pong operation. Thanks to the shifting capacitor providing voltage step between the OTA output and the inverter output, the suppressed inverter output swing helps OTA to achieve higher DC gain yielding better accuracy in the application of charge amplifier or integrator. The proposed technique utilizes two identical sub-OTA structures working in the ping-pong way to provide level shifting reference voltage for each other. This operation allows inverter-based OTA to work at the amplification mode in both clock phases, thus double sampling technique can be adopted to achieve twice of the charge transfer efficiency. Compared with the conventional inverter-based charge amplifier, the proposed topology improves DC gain from 39dB to 71dB at the cost of 17% power consumption increase from 7.1µA to 8.6µA.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"631 1","pages":"1-4"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77521965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 4Gbps DPPM On-chip Serial Link Based on Pipelined Vernier-Tdc","authors":"Jinhao Li, Chongbing Qu, Fan Wu, Jianfei Jiang","doi":"10.1109/ICSICT49897.2020.9278344","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278344","url":null,"abstract":"This paper presents a double-edge Pulse Position Modulation (DPPM) time-domain serial link for on-chip interconnect. The proposed design can achieve highspeed low-power interconnect with a lower operating frequency. The time-to-digital converter (TDC) based receiver is pipelined to achieve a throughput rate of as high as 4Gbps. The overall system is designed and simulated to achieve 4Gbps data rate with 171.2fJ/bit/mm energy dissipation for 10mm on-chip interconnect on 40nm SMIC CMOS process.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"39 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73378151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Impact of Process Variability on Threshold Voltage in JLAM-VSN-FET","authors":"Haofeng Jiang, Cong Li, Jia‐Min Guo, Fei-Chen Liu, Zeng-Guang Guo, Y. Zhuang","doi":"10.1109/ICSICT49897.2020.9278163","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278163","url":null,"abstract":"Vertically Stacked Nanosheet FET (VSN-FET) is considered to be the most promising device to replace FinFET beyond the 3nm node. The VSN-FET can be implemented in either inversion mode (IM) or junctionless mode (JL). In order to reduce the impact of process variations on VSN-FET without sacrificing device characteristics, a new junctionless accumulation mode (JLAM) VSN-FET is proposed in this paper. By using TCAD with a statistical impedance field method (sIFM), the process variations of VSN-FET in IM, JL, and JLAM are compared in terms of RDF, WFV, and OTV. The results show that JLAM-VSN-FET has a simpler process compared to IM-VSN-FET, and better variation immunity compared to JL-VSN-FET. Further simulations of JLAM-VSN-FET indicate that the increase of work function difference in gate metal grains leads to the degradation of σVth. Besides, the application of thicker physical gate oxide with higher-κ is confirmed to alleviate σVth_WFV. As device scaling down, nanosheet height and gate oxide thickness scaling leads to the reduction of σVth_RDF, whereas channel length and width scaling results in the degradation of σVth_RDF, σVth_OTV, and σVth_WFV.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"96 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80184125","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jun Liu, Lin Zhang, Yabo Ni, Jia Liu, Xianjie Wan, Yi Ding, D. Fu
{"title":"A Feedback Loop-based Timing Adaptive Corrected Circuit","authors":"Jun Liu, Lin Zhang, Yabo Ni, Jia Liu, Xianjie Wan, Yi Ding, D. Fu","doi":"10.1109/ICSICT49897.2020.9278233","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278233","url":null,"abstract":"This paper introduces a kind of timing adaptive corrected circuit, which quantifies the phase between data generating clock and sampling clock, compares the current phase with the target phase that meets the timing requirement, adjusts the delay of one clock based on the comparison results, and changes the current phase, forms a negative feedback loop. This technique allows the sampling timing to be always met and also compensates for sampling timing changes caused by changes in the external environment, thus achieving data transfer and synchronization at high speed. In the post-simulation the inputs are two 5GHz clocks with 0° initial phase, after the loop is stabilized, the phase between the two output clocks is locked to 90° to meet the target phase.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"83 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81338353","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Low Power, wide-band input buffer for 12bit 1GS/s ADC","authors":"Wenbin He, Ziwei Li, Fan Ye, Junyan Ren","doi":"10.1109/ICSICT49897.2020.9278237","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278237","url":null,"abstract":"A wide-band input buffer has become the design challenge for the power efficiency of an ADC system. Most of the state-of-the-arts take a relatively costly design effort to alleviate the channel-length modulation of the SF. This paper presents a low power and high linearity push-pull input buffer with replica source followers(SFs) for 1GS/s 12bit high resolution and high speed ADC. The prototype input buffer is designed in 28nm CMOS process, achieving 82.3dB SFDR with 1pF load and 1.8V output swing, consuming only 9.17mW under 1.8V supply.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"1 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81357312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ze Wang, Xinpeng Xing, Xueqian Shang, Yi Ke, Zhihua Wang
{"title":"A 10-bit 60MHz-BW Continuous-Time Delta-Sigma ADC for wireless applications in 40nm CMOS","authors":"Ze Wang, Xinpeng Xing, Xueqian Shang, Yi Ke, Zhihua Wang","doi":"10.1109/ICSICT49897.2020.9278153","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278153","url":null,"abstract":"In this paper, a 10-bit 60MHz-BW continuous-time (CT) Delta-Sigma ADC is presented. A 3rd-order 3-bit ADC architecture with Cascaded Integrators Feed-Forward (CIFF) is adopted for the consideration of speed, performance, stability, power consumption and tolerance to non-idealities. The feedback digital signal is delayed by one clock period to absorb excess loop delay (ELD), and a zero-order feedback path is added to retain the noise transfer function. Both two-stage feedforward-compensated and single-stage OTAs are designed in the analog loop filter. The front-end feedback DAC is design with large area to ensure 10-bit intrinsic linearity. The ADC is designed and simulated in 40nm CMOS process with a sampling frequency of 1.92GHz. The simulations show that the ADC achieves 69.6dB SNR and 64.7dB SNDR for 60MHz BW, with a power consumption of 31.6mW, corresponding to a FoM of 188fJ/Step.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"26 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"81670394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design and Implementation of Cryptographic Instruction Set","authors":"Mengni Bie, Wei Li, Tao Chen, Longmei Nan","doi":"10.1109/icsict49897.2020.9278206","DOIUrl":"https://doi.org/10.1109/icsict49897.2020.9278206","url":null,"abstract":"With the development of embedded devices, power consumption and area have gradually become the bottleneck restricting chip design. Chip designers are more concerned about how to achieve higher performance under limited area and power consumption. This paper analyzes the cryptographic operations of all types of cryptographic algorithms including grouping, sequence, hashing, and public key. Then we extracts fine-grained common logic, designs corresponding cryptographic arithmetic units, follows the RISC-V instruction set architecture, and designs cryptographic extended instruction sets. Ariane, a low-power general-purpose cryptographic processor, was selected for transformation, and a low-power, high-performance cryptographic processor core was designed. The logic synthesis is performed under the 55nm CMOS process, and the results show that we have exchanged for a higher cryptographic operation speed with an area overhead of 1162718.09 µm2 and a critical delay of 2.5 ns. And the experiments show that AES-128 takes about 290ns, and ECC in the 256-bit prime field takes about 0.224ms.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"113 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86271475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chi Liu, Wei Ma, Maolin Chen, W. Ren, Dongming Sun
{"title":"A Graphene Base Transistor for Potential Terahertz Application","authors":"Chi Liu, Wei Ma, Maolin Chen, W. Ren, Dongming Sun","doi":"10.1109/ICSICT49897.2020.9278222","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278222","url":null,"abstract":"Graphene base transistors have been proposed for THz applications, however, the so far employed tunnel emitter makes this goal challenging because that an emitter potential barrier as low as 0.4 eV is needed which is difficult to achieve. Here, we demonstrate a silicon-graphene-germanium graphene base transistor which employs a Schottky emitter. The Schottky emitter junction shows both a largest on-current and a smallest capacitance leading to about 1000 times improvement of the alpha cut-off frequency of the transistor compared with the ones with tunnel emitters. A THz application for the proposed transistor is expected by further engineering, and direction of future development is discussed.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"72 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86344335","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Improved SPICE Based Behavior Model for Non-Snapback TVS Devices with Ultra-low Turn-on Resistance","authors":"Yanlin Nie, Qiupei Huang, Jizhi Liu, Zhiwei Liu","doi":"10.1109/ICSICT49897.2020.9278131","DOIUrl":"https://doi.org/10.1109/ICSICT49897.2020.9278131","url":null,"abstract":"TVS devices have been widely used in portable devices to improve the ESD robustness in system level ESD test. TVS model with good accuracy is desirable in the system level ESD simulation. This paper presents an improved SPICE based behavior model for TVS with ultra-low turn-on resistance. Validation have been down for both quasi-static behavior and transient behavior.","PeriodicalId":6727,"journal":{"name":"2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT)","volume":"47 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2020-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82614342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}